Method 2026-07-22
Compute Leverage
Leverage over a frontier training run, measured as switching cost times redeployment time.
Leverage over a frontier training run, measured as switching cost times redeployment time.
Pinned viewEvery verdict below resolves against xAI’s run rather than the cross-run default. Read the full view.
The horizon slope. One line per leverage point of the frontier-AI compute stack, carried from its veto verdict at eighteen months — the window to field a new frontier run — to its verdict at five years, the window for structural independence. A holder gates a run when switching cost × redeployment time exceeds the horizon, not when it merely holds market share. Line weight carries the authority tier of the redeployment-time coefficient, the input the verdict turns on: solid at primary or research grade, lighter at press or analyst grade, dotted where no source was found. A hollow square marks a gate held by a coupled stack of institutions rather than a single firm. The verdicts drawn resolve against xAI’s run; the strip below shows the other two and the cross-run baseline. The honest limit: the five-year column is a judgement about how markets mature, not a measurement — four of the seven present gates resolve to uncertain rather than to a verdict.
Eleven leverage points stand between a lab and a trained frontier model. At eighteen months seven of them can gate a new run; at five years only two still can — EDA tools (chip design) and EUV lithography, where no commercial alternative exists at any horizon a Western lab could reach. Every one of the seven answers to some public lever, and the lever that reaches all seven is export control, which governs where a holder may sell — not whether it must sell to anyone in particular. It polices diversion, not allocation. The count is a barrier to entry: it gates who can start a frontier run, not who can halt one already under way.
| Leverage point | 18 months | 5 years | Checked by | Redeployment time |
|---|---|---|---|---|
| EUV lithography · ASML | can gate | can gate | Export control — A 100% monopoly, but governed by Dutch + US multilateral export-control law — a governance hook exists over the layer, so it is checked-in-principle rather than fully uncontested. | No commercial alternative at any horizon for a Western lab; state-built EUV at scale assessed 5-10+ years out · estimated |
| Advanced logic foundry (≤5nm/3nm) · TSMC, Samsung Foundry, Intel Foundry | can gate | uncertain | Export control — Leading-edge logic fabrication is governed by US export-control law: the Foreign Direct Product Rule reaches any chip made with US tooling, and the Jan-2025 Foundry Due-Diligence Rule mandates quarterly OSAT/foundry KYC compliance reporting to BIS — a public lever exists over the layer. | No published figure for a full TSMC→Samsung inter-foundry port of a leading-edge AI accelerator · no source found |
| EDA tools (chip design) · Synopsys, Cadence, Siemens EDA | can gate | can gate | Export control — EDA for leading-edge design is governed by US export-control law: BIS exercised a standing enforcement order (Cadence $95M penalty, 28 Jul 2025, for EDA exports to Entity-List parties NUDT/Phytium under EAR §744) — a public lever exists over the layer. The broader China-sales licensing letters to Synopsys/Cadence/Siemens (imposed 23 May 2025) were rescinded 2 Jul 2025 under the US–China framework, so the enforcement order, not the letters, is the live instrument. | No production leading-edge alternative at any horizon; a full design re-verification on a second toolchain has no qualified ≤7nm target. · no source found |
| HBM memory (HBM3E / HBM4) · SK Hynix, Samsung, Micron | can gate | cannot gate | Export control — HBM is governed by US export-control law — the Dec-2024 rule controls HBM at/above a bandwidth-density threshold (>2 GB/s/mm²), on top of the Oct-2022/Oct-2023 advanced-computing controls — a public lever exists over the layer. | 12-24 months to qualify a secondary supplier, anchored to the Samsung→NVIDIA case (~18-month qualification for a supplier with a finished product) · estimated |
| Advanced packaging / CoWoS · TSMC, OSATs (ASE, Amkor, SPIL) | can gate | uncertain | Export control — Since 16 Jan 2025, with compliance required from 31 Jan, a BIS regime reaches the packaging layer directly: the Foundry Due-Diligence Rule (90 FR 5298, FR Doc. 2025-00711) makes approved-OSAT attestations the mechanism by which packaged advanced ICs escape licensing presumptions, keeps the approved-OSAT list at Supplement No. 7 to Part 740, and requires quarterly OSAT/foundry compliance reporting — the same rule already cited on the advanced-foundry layer, whose named obligors include this layer’s own holders. The Dec-2024 rule separately controls advanced-packaging equipment. | New OSAT production line ~6-9 months; customer-level requalification for a given accelerator unverified · no source found |
| AI accelerator · NVIDIA, Google TPU, AWS Trainium, AMD | can gate | uncertain | Export control — Frontier AI accelerators are the primary object of US export-control law (ECCN 3A090/4A090; the Oct-2023 Total-Processing-Performance metric closed the A800/H800 work-arounds) — the most-governed layer in the stack. | Committed labs (CUDA-bespoke): >18 months. Diversified/vertically-integrated labs: already routed around NVIDIA at production scale (not applicable). · estimated |
| Scale-up interconnect (NVLink / NVSwitch) · NVIDIA | can gate | uncertain | Export control — Reached by the same US advanced-computing export-control architecture as the accelerator it binds: ECCN 3A090 has an I/O-bandwidth control parameter (≥150 GB/s aggregate bidirectional) and 4A090 covers electronic assemblies/components incorporating controlled accelerators (e.g. GB200 NVL72 racks) — the scale-up fabric is governed by the regime, not merely by an emerging market alternative. | No production UALink alternative until ~late 2026 at earliest (committed labs) · estimated |
| Scale-out interconnect (InfiniBand vs Ethernet) · NVIDIA/Mellanox InfiniBand, Broadcom/Arista Ethernet | cannot gate | cannot gate | Competition — Ethernet (Broadcom, Arista, Ultra Ethernet Consortium) is a production-scale alternative; demonstrated at frontier scale. | Routable to Ethernet now for a lab with fabric-engineering capacity · estimated |
| Cloud / datacenter capacity · AWS, Microsoft Azure, Google Cloud, CoreWeave, Oracle, neoclouds | uncertain | cannot gate | Competition — Capacity is fragmenting (97GW of new colocation projected 2025-30); multi-vendor structure means no single cloud provider is a unilateral veto for a top lab. | Binding for single-vendor-locked startups; not for multi-vendor pre-positioned labs · estimated |
| Power / grid interconnection · ISO/RTO (MISO, PJM, ERCOT, SPP), local utility, state PUC, FERC, EPA — a coupled stack of institutions, not one firm | cannot gate | uncertain | Public body — The veto-holders are public bodies (ISO/RTO, utilities, state PUCs, FERC, EPA) subject to democratic/regulatory/FOIA accountability — a DIFFERENT KIND of power than a private monopoly. | New site: ~4.5yr average to commercial operation (transformer ~160wk OR interconnection study alone exceeds 18 months). A well-capitalized lab can bypass the grid with on-site gas (the xAI Colossus route), so the new-site veto does not bind an incumbent already self-generating its power. · estimated |
| Capital ($1B+/yr runs) · hyperscaler balance sheets, sovereign funds (QIA, PIF, Mubadala), mega-VC | uncertain | cannot gate | Competition — Capital access is structurally expanding (sovereigns + infrastructure investors entering); diversified + compute-entangled funding means no single provider is a unilateral veto for a top lab. | No frontier-class lab was found single-funder-gated — the largest rounds are syndicates (Anthropic’s $30B Series G: 2 leads, 5 co-leads, ~30 named investors; OpenAI’s $122B round: 6 co-leads plus Amazon/NVIDIA/SoftBank/Microsoft); a single-funder veto is implausible for hyperscalers and multi-investor labs. · estimated |
Needs verificationThree redeployment-time coefficients — EDA tools (chip design), advanced logic foundry (≤5nm/3nm), advanced packaging / CoWoS — have no published figure behind them. Each is drawn dotted in the plate above and none of the three carries a verdict on its own: the eighteen-month gate at each rests on capacity or on the absence of a qualified alternative, both of which are sourced.
A gate binds a lab that cannot route around it, so the count is a property of the run as much as of the stack. Against the cross-run baseline of eight gates, a lab that designs its own accelerator and runs it on its own fabric clears the ones a CUDA-committed lab cannot.
A holder gates a run when switching cost × redeployment time exceeds the horizon — when the lab cannot route around it in time. Market share is shown as context and never decides a verdict: the scale-out interconnect layer is concentrated and gates nothing, because Ethernet is a real substitute a lab can adopt now, while advanced packaging has no published share split and gates at eighteen months because capacity is allocated years out.
Two horizons, because they answer different questions. Eighteen months is the window to field a new run; five years is the window for structural independence. A closing window reads can gate then cannot; a permanent lock reads can gate at both. How leverage is derived
Accountability is the strongest governance hook over the layer under a fixed priority order — export control, then antitrust, then a public body, then competition, then nothing — assigned per layer against a stated rule the reader can contest. Whether a competitor is reachable inside a horizon lives in the verdict, not the tag: an alternative that exists but cannot be switched to in eighteen months is a gate with a competition hook, not an absence of accountability.
7 of 11 layers are checked by export control, and that hook is directional. These regimes govern whom a holder may sell to — they police diversion. None of them obliges a holder to sell to any particular lab, so the lever that reaches furthest across this stack is not a lever on allocation. What each check can and cannot reach, layer by layer.