Cite this page Data files 27 of 31 accelerators with a calculable TPP reach the 4,800 threshold, and 7 of the 8 at or above 6,500 GB/s are recorded as restricted for China.
Oct 2022 Nov 2023 Dec 2024 Apr 2025 Jul 2025 Jan 2026
TPP 4,800, ECCN 3A090.a 6,500 GB/s DRAM bandwidth TPP 21,000 Conditional case-by-case review Presumption of denial 500 1,000 2,000 5,000 10,000 20,000 2,000 5,000 10,000 20,000 50,000 100,000 200,000 GB/s No memory bandwidth published A100 SXM, A800 H100 SXM5 H100 PCIe, H800 PCIe H100 NVL H800 SXM5 ~ H200 SXM H20 SXM ~ H20E ~ B100 B200 B30A ~ Rubin GPU ~ MI300X MI325X MI350X Ascend 910B ~ Gaudi 3 TPU v4 TPU v5e TPU v5p TPU v6e B300 MI355X MI400 ~ TPU v7 Trainium3 ~ Blackhole p150 Ascend 910C ~ Ascend 920 ~ Each accelerator’s Total Processing Performance (TPP) against its memory bandwidth, both axes logarithmic. Curves join compliance variants to their parent.
12 8 1 4 10 Selected rule: January 2026 License Review Policy Revision, effective 15 Jan 2026 .
Restricted12 Case-by-Case Review8 Designed Compliant1 Domestic (China)4 Unassessed10 Status glyphs retain the catalog’s recorded China assessment across every selected rule date. Hatched regions and threshold lines follow the selected rule; the separate rail holds chips with unpublished memory bandwidth.
31 accelerators with a calculable TPP. Select a chip to trace its position and open its specifications. Status marks and filters retain the catalog’s recorded China assessment across all rule dates.
January 2026 License Review Policy Revision . Newly restricted in this action: none recorded.
Threshold Move the TPP parameter to compare specifications; the recorded China status remains unchanged.
Total Processing Performance (log) → 10k 100k ECCN 3A090.a.1 threshold: TPP 4,800 TPP 4,800 · 3A090.a.1 H20 SXM (NVIDIA) · TPP 2,368 on the FP16 basis · estimated specification · Case-by-Case Review H20E (HBM3E refresh) (NVIDIA) · TPP 2,368 on the FP16 basis · estimated specification · Unassessed TPU v5e (Google) · TPP 3,152 on the BF16 basis · Unassessed Google TPU v4 (Google) · TPP 4,400 on the BF16 basis · Unassessed A100 SXM (NVIDIA) · TPP 4,992 on the FP16 basis · Case-by-Case Review A800 (NVIDIA) · TPP 4,992 on the FP16 basis · Restricted Tenstorrent Blackhole p150 (Tenstorrent) · TPP 5,312 on the FP8 basis · Unassessed Ascend 910B (Huawei) · TPP 6,000 on the FP16 basis · estimated specification · Domestic (China) Google TPU v5p (Google) · TPP 7,344 on the BF16 basis · Unassessed H100 PCIe (NVIDIA) · TPP 12,104 on the FP8 basis · Case-by-Case Review H800 PCIe (NVIDIA) · TPP 12,104 on the FP8 basis · Restricted Huawei Ascend 910C (Huawei) · TPP 12,480 on the BF16 basis · estimated specification · Domestic (China) H100 NVL (NVIDIA) · TPP 13,368 on the FP16 basis · Case-by-Case Review B30A (NVIDIA) · TPP 14,000 on the FP8 basis · estimated specification · Designed Compliant Huawei Ascend 920 (Huawei) · TPP 14,400 on the BF16 basis · estimated specification · Domestic (China) Google TPU v6e (Trillium) (Google) · TPP 14,688 on the BF16 basis · Unassessed H100 SXM5 (NVIDIA) · TPP 15,832 on the FP16 basis · Case-by-Case Review H800 SXM5 (NVIDIA) · TPP 15,832 on the FP16 basis · estimated specification · Restricted H200 SXM (NVIDIA) · TPP 15,832 on the FP16 basis · Case-by-Case Review AWS Trainium3 (Amazon) · TPP 20,160 on the FP8 basis · estimated specification · Unassessed MI300X (AMD) · TPP 20,919 on the INT8 basis · Case-by-Case Review MI325X (AMD) · TPP 20,919 on the FP8 basis · Case-by-Case Review B100 (NVIDIA) · TPP 28,000 on the FP16 basis · Restricted Gaudi 3 (Intel) · TPP 29,360 on the BF16 basis · Restricted B200 (NVIDIA) · TPP 36,000 on the FP16 basis · Restricted Google TPU v7 (Ironwood) (Google) · TPP 36,912 on the FP8 basis · Unassessed MI350X (AMD) · TPP 36,954 on the FP16 basis · Restricted AMD Instinct MI355X (AMD) · TPP 40,266 on the FP16 basis · Restricted NVIDIA B300 (NVIDIA) · TPP 60,000 on the FP4 basis · Restricted NVIDIA Rubin GPU (NVIDIA) · TPP 140,000 on the FP8 basis · estimated specification · Restricted AMD Instinct MI400 (AMD) · TPP 160,000 on the FP8 basis · estimated specification · Restricted Total Processing Performance (log) → 10k 100k ECCN 3A090.a.1 threshold: TPP 4,800 TPP 4,800 · 3A090.a.1 H20 SXM (NVIDIA) · TPP 2,368 on the FP16 basis · estimated specification · Case-by-Case Review H20E (HBM3E refresh) (NVIDIA) · TPP 2,368 on the FP16 basis · estimated specification · Unassessed TPU v5e (Google) · TPP 3,152 on the BF16 basis · Unassessed Google TPU v4 (Google) · TPP 4,400 on the BF16 basis · Unassessed A100 SXM (NVIDIA) · TPP 4,992 on the FP16 basis · Case-by-Case Review A800 (NVIDIA) · TPP 4,992 on the FP16 basis · Restricted Tenstorrent Blackhole p150 (Tenstorrent) · TPP 5,312 on the FP8 basis · Unassessed Ascend 910B (Huawei) · TPP 6,000 on the FP16 basis · estimated specification · Domestic (China) Google TPU v5p (Google) · TPP 7,344 on the BF16 basis · Unassessed H100 PCIe (NVIDIA) · TPP 12,104 on the FP8 basis · Case-by-Case Review H800 PCIe (NVIDIA) · TPP 12,104 on the FP8 basis · Restricted Huawei Ascend 910C (Huawei) · TPP 12,480 on the BF16 basis · estimated specification · Domestic (China) H100 NVL (NVIDIA) · TPP 13,368 on the FP16 basis · Case-by-Case Review B30A (NVIDIA) · TPP 14,000 on the FP8 basis · estimated specification · Designed Compliant Huawei Ascend 920 (Huawei) · TPP 14,400 on the BF16 basis · estimated specification · Domestic (China) Google TPU v6e (Trillium) (Google) · TPP 14,688 on the BF16 basis · Unassessed H100 SXM5 (NVIDIA) · TPP 15,832 on the FP16 basis · Case-by-Case Review H800 SXM5 (NVIDIA) · TPP 15,832 on the FP16 basis · estimated specification · Restricted H200 SXM (NVIDIA) · TPP 15,832 on the FP16 basis · Case-by-Case Review AWS Trainium3 (Amazon) · TPP 20,160 on the FP8 basis · estimated specification · Unassessed MI300X (AMD) · TPP 20,919 on the INT8 basis · Case-by-Case Review MI325X (AMD) · TPP 20,919 on the FP8 basis · Case-by-Case Review B100 (NVIDIA) · TPP 28,000 on the FP16 basis · Restricted Gaudi 3 (Intel) · TPP 29,360 on the BF16 basis · Restricted B200 (NVIDIA) · TPP 36,000 on the FP16 basis · Restricted Google TPU v7 (Ironwood) (Google) · TPP 36,912 on the FP8 basis · Unassessed MI350X (AMD) · TPP 36,954 on the FP16 basis · Restricted AMD Instinct MI355X (AMD) · TPP 40,266 on the FP16 basis · Restricted NVIDIA B300 (NVIDIA) · TPP 60,000 on the FP4 basis · Restricted NVIDIA Rubin GPU (NVIDIA) · TPP 140,000 on the FP8 basis · estimated specification · Restricted AMD Instinct MI400 (AMD) · TPP 160,000 on the FP8 basis · estimated specification · Restricted Threshold: TPP 4,800
At the 3A090.a.1 threshold.
27 of 31
Accelerators with a calculable TPP meet or exceed this threshold.
16
Accelerators above the threshold with a recorded China status other than “Restricted” (ringed) — Case-by-Case Review: A100 SXM, H100 PCIe, H100 NVL, H100 SXM5, H200 SXM, MI300X; and 10 more.
Nearest below the line: TPU v4 at TPP 4,400 (8.3% below the parameter). Nearest above: A100 SXM at TPP 4,992 (4% above the parameter).
Specifications All published precisions, measurement scope, sources, status conditions and recorded deployment joins remain in each chip’s details.
Among parts with published dense FP16/BF16 throughput and off-die memory bandwidth, the highest Chinese domestic reading is 900 TFLOPS, compared with 4,000 TFLOPS across vendors.
All statuses Restricted (12) Case-by-Case Review (8) Designed Compliant (1) Domestic (China) (4) Unassessed (10) All vendors AMD (5) Amazon (1) Cerebras (1) Google (5) Huawei (4) Intel (2) NVIDIA (15) Tenstorrent (2) 35 of 35 accelerators Sort by Chip, A to Z Chip, Z to A Vendor, A to Z Vendor, Z to A Dense FP16/BF16, highest first Dense FP16/BF16, lowest first Memory bandwidth, highest first Memory bandwidth, lowest first China status, Restricted first China status, Unassessed first
Additional statuses under “Show all”: Designed Compliant (1), Domestic (China) (4), Unassessed (10)
Parts outside the per-IC plane: Gaudi 2 (No evaluable dense specification); Cerebras WSE-3 (Wafer-scale system; not plotted) ; Tenstorrent Wormhole n300 (Two-chip board totals; not plotted) ; Huawei Ascend 910D (No evaluable dense specification) .
Families Models left to right in catalogue order. An arc joins a compliance variant to its parent; the family name opens the recorded changes.
6 of 35 accelerators were designed as compliance variants.
H20 SXM has 148 dense TFLOPS, compared with 989.5 for H100 SXM5. Memory bandwidth is 4,000 GB/s against 3,350 GB/s.
A800 / A100 SXM and H800 PCIe / H100 PCIe publish the same dense compute and memory bandwidth; their marks are nested on the plane.
A100 SXM , A800
A800 reduced A100 interconnect bandwidth while retaining its compute throughput. The October 2023 revision removed interconnect bandwidth as a control parameter and restricted A800.
H100 SXM5 , H100 PCIe , H100 NVL , H800 SXM5 , H800 PCIe , H200 SXM , H20 SXM , H20E (HBM3E refresh)
H800 reduced interconnect bandwidth; H20 instead reduced compute while retaining substantial memory and interconnect bandwidth. The policy history includes restrictions on H800, a separate H20 licensing requirement and conditional case-by-case review for H200. Model details distinguish these actions and their dates.
B100 , B200 , NVIDIA B300 , B30A
B100 and B200 differ in power and throughput. B300 Blackwell Ultra raises dense FP4 throughput and memory capacity; B30A was reported as a proposed single-die variant for China, with specifications that remain estimates.
NVIDIA Rubin GPU
Rubin GPU preliminary individual-GPU specifications: 35 PFLOPS dense NVFP4 training, 17.5 PFLOPS dense FP8/FP6 training, 4 PFLOPS dense FP16/BF16, 288 GB HBM4 at 22 TB/s, and 3.6 TB/s NVLink. NVIDIA marks the figures as up to and subject to change.
MI300X , MI325X , MI350X , AMD Instinct MI355X , AMD Instinct MI400
MI325X expands memory relative to MI300X. The CDNA 4 MI350X and MI355X differ in cooling and throughput: MI350X is air-cooled, MI355X liquid-cooled. Their datasheets distinguish dense from sparse performance; the table uses dense values. MI400 specifications remain estimates from AMD’s June 2025 announcement.
Ascend 910B , Huawei Ascend 910C , Huawei Ascend 910D , Huawei Ascend 920
The 910B entry represents CSET’s 910B2 variant. The 910C estimate differs from Epoch AI’s reported throughput; 910D lacks numerical compute specifications here. The cited 920 report describes a projected launch. These differences in evidence limit comparisons across the family.
Gaudi 2 , Gaudi 3
Gaudi 2 and Gaudi 3 use Ethernet interconnects. Gaudi 3 combines TSMC N5 compute dies with Intel EMIB packaging. Its OAM and PCIe variants have different power ratings; this table represents the OAM variant.
AWS Trainium3
Trainium3 powers EC2 Trn3 UltraServers, which AWS announced as generally available in December 2025. Access is offered through AWS services. Per-chip power is not supplied in the cited announcement.
Cerebras WSE-3
WSE-3 uses wafer-scale integration and on-wafer SRAM. Its wafer-wide compute and bandwidth figures require separate treatment from per-GPU specifications.
Tenstorrent Wormhole n300 , Tenstorrent Blackhole p150
Wormhole n300 is a dual-ASIC PCIe card. Blackhole p150 uses the second-generation Tensix architecture with Ethernet scale-out. Its published compute figure uses BLOCKFP8; no dense FP16/BF16 figure is held here.
Rules Dated control actions from the existing catalog. Open a rule for its recorded threshold, newly restricted chips and cited documents.
21 Oct 2022 Compute performance (TFLOPS) and interconnect bandwidth
ECCN 3A090 combined an aggregate bidirectional transfer rate of at least 600 GB/s to or from other ICs, excluding volatile memories, with compute criteria equivalent to at least 4,800 bits × TOPS. Both bandwidth and compute conditions had to be met.
Newly restricted: A100 SXM , H100 SXM5 .
87 FR 62186 17 Nov 2023 Total Processing Performance (TPP): 2 × MacTOPS × bit-length, summed across processing units
Introduced the TPP metric — dense throughput × bit-length of the operation, evaluated at the highest value across supported bit-lengths, dense matrices only. Also broadened end-use controls. 3A090.a also has a second leg (TPP ≥ 1,600 with performance density ≥ 5.92) that requires applicable die area, which no record here publishes.
Newly restricted: A800 , H800 SXM5 , H800 PCIe .
88 FR 73458 2 Dec 2024 HBM memory bandwidth density
Added ECCN 3A090.c for HBM above 2 GB/s/mm² of memory bandwidth density, calculated from package or stack bandwidth and area. Certain co-packaged HBM-and-logic ICs whose dominant function is processing are excluded. The rule took effect December 2; compliance with the HBM provisions began December 31, 2024.
No newly restricted chips are recorded here for this action.
89 FR 96790 9 Apr 2025 No new threshold metric. License-required determination on the previously-compliant-by-design H20.
NVIDIA reported an April 9 government notice requiring licenses for H20 and other ICs meeting specified H20 bandwidth characteristics. It covered exports to China, including Hong Kong and Macau, D:5 countries, and companies headquartered or with an ultimate parent there. NVIDIA disclosed the notice on April 15.
Newly restricted: H20 SXM
NVIDIA Form 8-K 14 Jul 2025 Announcement of expected licensing; no technical threshold change.
NVIDIA announced assurances that licenses would be granted. Its August 2025 filing later confirmed licenses for selected H20 customers, and described a 15% revenue-share expectation from U.S. officials with no codifying regulation at that time.
No newly restricted chips are recorded here for this action.
NVIDIA announcement NVIDIA August 2025 filing 15 Jan 2026 TPP below 21,000 and total DRAM bandwidth below 6,500 GB/s: the ceilings for conditional case-by-case review.
Provides case-by-case review for qualifying US exports to China or Macau below 21,000 TPP and 6,500 GB/s total DRAM bandwidth. H200 and MI325X are examples. Approval depends on the rule’s supply, aggregate-TPP, end-use, security and testing conditions.
No newly restricted chips are recorded here for this action.
91 FR 1684 A100 SXM FP16 dense 312 TFLOPS
FP16 sparse 624 TFLOPS
BF16 dense 312 TFLOPS
TF32 dense 156 TFLOPS
TF32 sparse 312 TFLOPS
FP8 dense —
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 624 TOPS
Memory 80 GB HBM2e
Memory bandwidth 2,039 GB/s
Interconnect bandwidth 600 GB/s
Thermal design power 400 W
Process node TSMC 7nm
Architecture Ampere
Compliance variant of —
Total Processing Performance 4,992 (FP16 × bit-length; ≈1.04× the 3A090.a parameter)
Regulatory basis Licence required since the October 2022 rule (87 FR 62186). Under the January 2026 rule, qualifying US exports to China or Macau are reviewed case by case: its TPP of 4,992 and memory bandwidth of 2,039 GB/s are below the rule’s ceilings of 21,000 and 6,500 GB/s.
Status source Conditions Subject to the same aggregate-TPP cap and additional application requirements as H200; see the cited rule.
Source Primary source NVIDIA A100 datasheet — open
Notes FP16/BF16 Tensor Core dense = 312 TFLOPS; with 2:4 sparsity = 624 TFLOPS. TF32 dense = 156; sparse = 312. 80GB HBM2e variant.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Country access Covered in 3 of the 26 country access profiles — 1 available (United States) , 1 case-by-case (China) , 1 restricted (Russia) ; see country access profiles .
A800 FP16 dense 312 TFLOPS
FP16 sparse 624 TFLOPS
BF16 dense 312 TFLOPS
TF32 dense 156 TFLOPS
TF32 sparse 312 TFLOPS
FP8 dense —
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 624 TOPS
Memory 80 GB HBM2e
Memory bandwidth 2,039 GB/s
Interconnect bandwidth 400 GB/s
Thermal design power 400 W
Process node TSMC 7nm
Architecture Ampere
Compliance variant of A100 SXM
Total Processing Performance 4,992 (FP16 × bit-length; ≈1.04× the 3A090.a parameter)
Regulatory basis October 2023 rule (88 FR 73458): revised TPP and performance-density criteria under ECCN 3A090. Its TPP and memory bandwidth are below the January 2026 rule’s ceilings, but BIS limits that rule to chips commercially available in the United States when it was published, and caps exports to China at half of the same chip’s US shipments; this variant was built to pass the October 2022 rule for export to China, and no US sales of it are recorded here, so the presumption of denial stands.
Source Research database NVIDIA / Tom's Hardware analysis — open
Notes Same compute cores as A100 (FP16 dense 312 TFLOPS). Only NVLink bandwidth reduced (600→400 GB/s). Was compliant under Oct 2022 rule; restricted by Oct 2023 TPP metric.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
H100 SXM5 FP16 dense 989.5 TFLOPS
FP16 sparse 1,979 TFLOPS
BF16 dense 989.5 TFLOPS
TF32 dense 494.7 TFLOPS
TF32 sparse 989.5 TFLOPS
FP8 dense 1,979 TFLOPS
FP8 sparse 3,958 TFLOPS
FP4 dense —
FP4 sparse —
INT8 1,979 TOPS
Memory 80 GB HBM3
Memory bandwidth 3,350 GB/s
Interconnect bandwidth 900 GB/s
Thermal design power 700 W
Process node TSMC 4N
Architecture Hopper
Compliance variant of —
Total Processing Performance 15,832 (FP16 × bit-length; ≈3.3× the 3A090.a parameter)
Regulatory basis Licence required since the October 2022 rule (87 FR 62186). Under the January 2026 rule, qualifying US exports to China or Macau are reviewed case by case: its TPP of 15,832 and memory bandwidth of 3,350 GB/s are below the rule’s ceilings of 21,000 and 6,500 GB/s.
Status source Conditions Subject to the same aggregate-TPP cap and additional application requirements as H200; see the cited rule.
Source Primary source NVIDIA H100 datasheet — open
Notes FP16/BF16 Tensor Core throughput is 989.5 TFLOPS dense or 1,979 TFLOPS with 2:4 sparsity. TF32 is 494.7 dense or 989.5 sparse. Epoch AI lists 989.4 dense TFLOPS; the table uses the NVIDIA figure.
Recorded deployments This accelerator appears at 2 of the 9 facilities with GPU inventories: xAI Colossus Memphis Phase 3 — 150,000 × NVIDIA H100 SXM5 80GB; OpenAI/Microsoft Goodyear Arizona — 100,000 × NVIDIA H100 SXM5 80GB (estimated) . Inventory names are preserved. A name is matched to a part only through whole words, so a board such as GB200 is not matched to B200.
Country access Covered in 26 of the 26 country access profiles — 20 available , 2 case-by-case (Saudi Arabia, China) , 4 restricted (Russia, Iran, North Korea, Belarus) ; see country access profiles .
H100 PCIe FP16 dense 756 TFLOPS
FP16 sparse 1,513 TFLOPS
BF16 dense 756 TFLOPS
TF32 dense 378.7 TFLOPS
TF32 sparse 756 TFLOPS
FP8 dense 1,513 TFLOPS
FP8 sparse 3,026 TFLOPS
FP4 dense —
FP4 sparse —
INT8 1,513 TOPS
Memory 80 GB HBM2e
Memory bandwidth 2,000 GB/s
Interconnect bandwidth —
Thermal design power 350 W
Process node TSMC 4N
Architecture Hopper
Compliance variant of —
Total Processing Performance 12,104 (FP8 × bit-length; ≈2.52× the 3A090.a parameter)
Regulatory basis Licence required since the October 2022 rule (87 FR 62186). Under the January 2026 rule, qualifying US exports to China or Macau are reviewed case by case: its TPP of 12,104 and memory bandwidth of 2,000 GB/s are below the rule’s ceilings of 21,000 and 6,500 GB/s.
Status source Conditions Subject to the same aggregate-TPP cap and additional application requirements as H200; see the cited rule.
Source Primary source NVIDIA H100 PCIe GPU Product Brief PB-11133-001 (November 2022) — the original 80 GB HBM2e PCIe variant superseded by H100 NVL on the current NVIDIA product page — open
Notes Original 80 GB HBM2e PCIe variant, documented in NVIDIA product brief PB-11133-001. Dense FP16/BF16 throughput is 756 TFLOPS at 350 W. The H100 NVL has a separate row with 94 GB HBM3; its specifications should not be substituted for this model.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
H100 NVL FP16 dense 835.5 TFLOPS
FP16 sparse 1,671 TFLOPS
BF16 dense 835.5 TFLOPS
TF32 dense 417.75 TFLOPS
TF32 sparse 835.5 TFLOPS
FP8 dense 1,671 TFLOPS
FP8 sparse 3,341 TFLOPS
FP4 dense —
FP4 sparse —
INT8 1,671 TOPS
Memory 94 GB HBM3
Memory bandwidth 3,938 GB/s
Interconnect bandwidth 600 GB/s
Thermal design power 400 W
Process node TSMC 4N
Architecture Hopper
Compliance variant of —
Total Processing Performance 13,368 (FP16 × bit-length; ≈2.79× the 3A090.a parameter)
Regulatory basis Licence required since the October 2022 rule (87 FR 62186). Under the January 2026 rule, qualifying US exports to China or Macau are reviewed case by case: its TPP of 13,368 and memory bandwidth of 3,938 GB/s are below the rule’s ceilings of 21,000 and 6,500 GB/s.
Status source Conditions Subject to the same aggregate-TPP cap and additional application requirements as H200; see the cited rule.
Source Primary source NVIDIA H100 NVL Product Brief PB-11773-001 (March 2024) + current NVIDIA H100 product page — open
Notes H100 NVL has 94 GB HBM3 per GPU, or 188 GB per pair. The March 2024 product brief reports 3,938 GB/s memory bandwidth and configurable power of 350–400 W. The table uses 835.5 dense FP16/BF16 TFLOPS per GPU; earlier launch figures were higher.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
H800 SXM5 FP16 dense ~ 989.5 TFLOPS
FP16 sparse ~ 1,979 TFLOPS
BF16 dense ~ 989.5 TFLOPS
TF32 dense ~ 494.7 TFLOPS
TF32 sparse ~ 989.5 TFLOPS
FP8 dense ~ 1,979 TFLOPS
FP8 sparse ~ 3,958 TFLOPS
FP4 dense —
FP4 sparse —
INT8 ~ 1,979 TOPS
Memory ~ 80 GB
Memory bandwidth —
Interconnect bandwidth ~ 400 GB/s
Thermal design power ~ 700 W
Process node TSMC 4N
Architecture Hopper
Compliance variant of H100 SXM5
Total Processing Performance ~ 15,832 (FP16 × bit-length; ≈3.3× the 3A090.a parameter)
Regulatory basis October 2023 rule (88 FR 73458): revised TPP and performance-density criteria under ECCN 3A090. Its TPP and memory bandwidth are below the January 2026 rule’s ceilings, but BIS limits that rule to chips commercially available in the United States when it was published, and caps exports to China at half of the same chip’s US shipments; this variant was built to pass the October 2022 rule for export to China, and no US sales of it are recorded here, so the presumption of denial stands.
Status source Source Research database NVIDIA / tier-2 technical analysis (no public NVIDIA H800 SXM5 datasheet exists) — open
Notes H800 SXM5 retains H100 SXM5 compute throughput while reducing NVLink from 900 to 400 GB/s. Secondary sources disagree on memory bandwidth: technical.city and gpus.axiomgaming report about 1,681 GB/s; router-switch reports about 3,361 GB/s. Memory bandwidth is left unavailable pending resolution. The available specifications are from secondary reporting, rather than an NVIDIA product brief.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
H800 PCIe FP16 dense 756 TFLOPS
FP16 sparse 1,513 TFLOPS
BF16 dense 756 TFLOPS
TF32 dense 378.7 TFLOPS
TF32 sparse 756 TFLOPS
FP8 dense 1,513 TFLOPS
FP8 sparse 3,026 TFLOPS
FP4 dense —
FP4 sparse —
INT8 1,513 TOPS
Memory 80 GB HBM2e
Memory bandwidth 2,000 GB/s
Interconnect bandwidth 400 GB/s
Thermal design power 350 W
Process node TSMC 4N
Architecture Hopper
Compliance variant of H100 PCIe
Total Processing Performance 12,104 (FP8 × bit-length; ≈2.52× the 3A090.a parameter)
Regulatory basis October 2023 rule (88 FR 73458): revised TPP and performance-density criteria under ECCN 3A090. Its TPP and memory bandwidth are below the January 2026 rule’s ceilings, but BIS limits that rule to chips commercially available in the United States when it was published, and caps exports to China at half of the same chip’s US shipments; this variant was built to pass the October 2022 rule for export to China, and no US sales of it are recorded here, so the presumption of denial stands.
Status source Source Primary source Lenovo ThinkSystem NVIDIA H800 PCIe Gen5 GPU product guide (lp1814) — open
Notes The Lenovo product guide specifies 80 GB HBM2e, 2 TB/s memory bandwidth, 350 W power and a 400 GB/s NVLink bridge. Dense FP16 throughput is 756 TFLOPS, matching H100 PCIe. These specifications apply to the PCIe model; H800 SXM5 has a separate row.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
H200 SXM FP16 dense 989.5 TFLOPS
FP16 sparse 1,979 TFLOPS
BF16 dense 989.5 TFLOPS
TF32 dense 494.7 TFLOPS
TF32 sparse 989.5 TFLOPS
FP8 dense 1,979 TFLOPS
FP8 sparse 3,958 TFLOPS
FP4 dense —
FP4 sparse —
INT8 1,979 TOPS
Memory 141 GB HBM3E
Memory bandwidth 4,800 GB/s
Interconnect bandwidth 900 GB/s
Thermal design power 700 W
Process node TSMC 4N
Architecture Hopper
Compliance variant of —
Total Processing Performance 15,832 (FP16 × bit-length; ≈3.3× the 3A090.a parameter)
Regulatory basis January 2026 rule: case-by-case review for qualifying US exports to China or Macau.
Status source Conditions Conditions include a cap on aggregate TPP exported to China/Macau: at most 50% of TPP shipped to US customers for US end-use for the same commodities, from first commercial US shipment through application. Supply, end-use, security and independent US testing requirements also apply.
Source Primary source NVIDIA H200 datasheet; BIS Jan 2026 press release — open
Notes Same compute die as H100 (FP16 dense 989.5 TFLOPS). 141 GB HBM3E at 4,800 GB/s. Jan 2026 policy shifted from presumption of denial to case-by-case review with material conditions.
Recorded deployments This accelerator appears at 1 of the 9 facilities with GPU inventories: xAI Colossus Memphis Phase 3 — 50,000 × NVIDIA H200 SXM
Country access Covered in 23 of the 26 country access profiles — 20 available , 2 case-by-case (Saudi Arabia, China) , 1 restricted (Russia) ; see country access profiles .
H20 SXM FP16 dense ~ 148 TFLOPS
FP16 sparse ~ 296 TFLOPS
BF16 dense ~ 148 TFLOPS
TF32 dense ~ 74 TFLOPS
TF32 sparse ~ 148 TFLOPS
FP8 dense ~ 296 TFLOPS
FP8 sparse ~ 592 TFLOPS
FP4 dense —
FP4 sparse —
INT8 ~ 296 TOPS
Memory ~ 96 GB
Memory bandwidth ~ 4,000 GB/s
Interconnect bandwidth ~ 900 GB/s
Thermal design power ~ 400 W
Process node TSMC 4N
Architecture Hopper
Compliance variant of H100 SXM5
Total Processing Performance ~ 2,368 (FP16 × bit-length; ≈0.493× the 3A090.a parameter)
Regulatory basis NVIDIA reports that U.S. licenses for selected H20 sales began in August 2025.
Status source Conditions NVIDIA’s August 2026 filing says Chinese government restrictions prevented it from selling its H20 inventory despite those licenses.
Source Press or analyst IFP "The H20 Problem" (Apr 2025) + Tom's Hardware H20 reporting + Flopper.io spec sheet + Baidu Baike English mirror + SemiAnalysis (Nov 2023). NO public NVIDIA H20 datasheet exists — H20 is sold via Chinese OEM channels (H3C / Inspur / Sugon) only. — open
Notes Hopper compliance variant designed after the October 2023 rule. Reported specifications include 96 GB HBM3, 4 TB/s memory bandwidth and 900 GB/s NVLink. The figures come from secondary sources. Sparse throughput values are derived by applying a 2× multiplier to dense throughput; they are not separately reported measurements.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
H20E (HBM3E refresh) FP16 dense ~ 148 TFLOPS
FP16 sparse ~ 296 TFLOPS
BF16 dense ~ 148 TFLOPS
TF32 dense ~ 74 TFLOPS
TF32 sparse ~ 148 TFLOPS
FP8 dense ~ 296 TFLOPS
FP8 sparse ~ 592 TFLOPS
FP4 dense —
FP4 sparse —
INT8 ~ 296 TOPS
Memory ~ 144 GB
Memory bandwidth —
Interconnect bandwidth ~ 900 GB/s
Thermal design power ~ 400 W
Process node TSMC 4N
Architecture Hopper
Compliance variant of H100 SXM5
Total Processing Performance ~ 2,368 (FP16 × bit-length; ≈0.493× the 3A090.a parameter)
Regulatory basis The reported relationship to H20 does not establish a licensing status for this variant. NVIDIA’s cited filing describes H20 licensing without separately naming H20E; variant-specific approval is unverified.
Status source Conditions The reported memory increase does not establish whether a particular H20 license covers this variant.
Source Press or analyst TweakTown and ChinaTalk reporting on H20E (2025) — open
Notes Reported H20 refresh with 144 GB HBM3E, compared with 96 GB on H20. Compute throughput is recorded as unchanged. The cited reporting does not establish memory bandwidth, so that value is left unavailable.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
B100 FP16 dense 1,750 TFLOPS
FP16 sparse 3,500 TFLOPS
BF16 dense 1,750 TFLOPS
TF32 dense 875 TFLOPS
TF32 sparse 1,750 TFLOPS
FP8 dense 3,500 TFLOPS
FP8 sparse 7,000 TFLOPS
FP4 dense 7,000 TFLOPS
FP4 sparse 14,000 TFLOPS
INT8 3,500 TOPS
Memory 192 GB HBM3E
Memory bandwidth 8,000 GB/s
Interconnect bandwidth 1,800 GB/s
Thermal design power 700 W
Process node TSMC 4NP
Architecture Blackwell
Compliance variant of —
Total Processing Performance 28,000 (FP16 × bit-length; ≈5.83× the 3A090.a parameter)
Regulatory basis Exceeds TPP threshold and DRAM bandwidth threshold (6,500 GB/s). No case-by-case pathway for Blackwell-class.
Source Research database NVIDIA Blackwell Architecture announcement (GTC 2024); Tom's Hardware GTC 2024 coverage — open
Notes 700W variant of Blackwell (drop-in HGX H100 compatible). Per GTC 2024 announcement: FP16/BF16 dense 1,750 TFLOPS / sparse 3,500; FP8 dense 3,500 / sparse 7,000; FP4 dense 7,000 / sparse 14,000. 192 GB HBM3E (8×24 GB) at 8 TB/s; NVLink 1.8 TB/s. B100 ≈ 78% of B200 dense throughput (1,750 / 2,250). NVIDIA does not publish a standalone B100 datasheet; specs come from the GTC 2024 launch slide deck and Blackwell architecture brief.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
B200 FP16 dense 2,250 TFLOPS
FP16 sparse 4,500 TFLOPS
BF16 dense 2,250 TFLOPS
TF32 dense 1,125 TFLOPS
TF32 sparse 2,250 TFLOPS
FP8 dense 4,500 TFLOPS
FP8 sparse 9,000 TFLOPS
FP4 dense 9,000 TFLOPS
FP4 sparse 18,000 TFLOPS
INT8 4,500 TOPS
Memory 192 GB HBM3E
Memory bandwidth 8,000 GB/s
Interconnect bandwidth 1,800 GB/s
Thermal design power 1,000 W
Process node TSMC 4NP
Architecture Blackwell
Compliance variant of —
Total Processing Performance 36,000 (FP16 × bit-length; ≈7.5× the 3A090.a parameter)
Regulatory basis Exceeds TPP threshold (21,000) and DRAM bandwidth threshold (6,500 GB/s). No case-by-case pathway for Blackwell-class.
Source Primary source NVIDIA Blackwell Architecture Technical Brief; HGX B200 1000W variant — open
Notes Specifications apply to the 1,000 W HGX B200 variant. Per GPU, FP16/BF16 throughput is 2,250 TFLOPS dense or 4,500 with sparsity; FP4 is 9,000 dense or 18,000 sparse. GB200 configurations use different specifications. Memory bandwidth is 8,000 GB/s.
Recorded deployments This accelerator appears at 1 of the 9 facilities with GPU inventories: OpenAI/Microsoft Atlanta — 300,000 × NVIDIA B200 (estimated)
Country access Covered in 25 of the 26 country access profiles — 20 available , 5 restricted ; see country access profiles .
B30A FP16 dense —
FP16 sparse ~ 900 TFLOPS
BF16 dense —
TF32 dense —
TF32 sparse —
FP8 dense ~ 1,750 TFLOPS
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 —
Memory ~ 144 GB
Memory bandwidth —
Interconnect bandwidth —
Thermal design power —
Process node TSMC (node unconfirmed)
Architecture Blackwell
Compliance variant of B200
Total Processing Performance ~ 14,000 (FP8 × bit-length; ≈2.92× the 3A090.a parameter)
Regulatory basis Designed to fall below BIS Performance Density thresholds. No formal BIS ruling as of Q3 2025. Jensen Huang (Aug 2025): "That's not our decision to make. It's up to the United States government."
Source Estimated TrendForce (Aug 2025) — industry primary covering NVIDIA China-focused Blackwell development — open
Notes TrendForce reported a proposed single-die Blackwell variant for China in August 2025, with 144 GB HBM3E and roughly half of B300 performance. It described possible test samples for September 2025. Compute and power specifications here remain unverified industry estimates; this report does not establish later product availability.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
NVIDIA Rubin GPU FP16 dense ~ 4,000 TFLOPS
FP16 sparse —
BF16 dense ~ 4,000 TFLOPS
TF32 dense ~ 2,000 TFLOPS
TF32 sparse —
FP8 dense ~ 17,500 TFLOPS
FP8 sparse —
FP4 dense ~ 35,000 TFLOPS
FP4 sparse —
INT8 ~ 250 TOPS
Memory ~ 288 GB
Memory bandwidth ~ 22,000 GB/s
Interconnect bandwidth ~ 3,600 GB/s
Thermal design power —
Process node —
Architecture Rubin
Compliance variant of —
Total Processing Performance ~ 140,000 (FP8 × bit-length; ≈29.2× the 3A090.a parameter)
Regulatory basis Preliminary NVIDIA individual-GPU specifications yield TPP 140,000 (17,500 dense FP8 TFLOPS × 8 bits, tied by 35,000 dense FP4 TFLOPS × 4 bits), above the 4,800 3A090.a parameter.
Source Primary source NVIDIA HGX Rubin individual-GPU specifications (preliminary) — open
Notes NVIDIA labels these individual-GPU specifications preliminary and subject to change. Dense training throughput is 35 PFLOPS at NVFP4, 17.5 at FP8/FP6 and 4 at FP16/BF16. Its separate 50 PFLOPS NVFP4 inference with sparse processing is excluded from TPP because the calculation uses dense throughput. The checked table supplies no per-GPU power or process-node figure.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
MI300X FP16 dense 1,307.4 TFLOPS
FP16 sparse 2,614.9 TFLOPS
BF16 dense 1,307.4 TFLOPS
TF32 dense —
TF32 sparse —
FP8 dense 1,307.4 TFLOPS
FP8 sparse 2,614.9 TFLOPS
FP4 dense —
FP4 sparse —
INT8 2,614.9 TOPS
Memory 192 GB HBM3
Memory bandwidth 5,300 GB/s
Interconnect bandwidth —
Thermal design power 750 W
Process node TSMC 5nm/6nm
Architecture CDNA3
Compliance variant of —
Total Processing Performance 20,919.2 (INT8 × bit-length; ≈4.36× the 3A090.a parameter)
Regulatory basis Licence required under ECCN 3A090.a as revised by the October 2023 rule (88 FR 73458). Under the January 2026 rule, qualifying US exports to China or Macau are reviewed case by case: its TPP of 20,919 and memory bandwidth of 5,300 GB/s are below the rule’s ceilings of 21,000 and 6,500 GB/s.
Status source Conditions Subject to the same aggregate-TPP cap and additional application requirements as H200; see the cited rule.
Source Primary source AMD MI300X datasheet — open
Notes AMD CDNA3 matrix engines deliver 1,307.4 FP16 TFLOPS dense (without 2:4 sparsity); 2,614.9 with sparsity. FP8 follows the same dense/sparse pair: 1,307.4 dense / 2,614.9 sparse per AMD MI300X data sheet. AMD does not report TF32. Uses Infinity Fabric interconnect.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Country access Covered in 6 of the 26 country access profiles — 4 available (United States, United Kingdom, Japan, South Korea) , 1 case-by-case (China) , 1 restricted (Russia) ; see country access profiles .
MI325X FP16 dense 1,307.4 TFLOPS
FP16 sparse 2,614.9 TFLOPS
BF16 dense 1,307.4 TFLOPS
TF32 dense 653.7 TFLOPS
TF32 sparse 1,307.4 TFLOPS
FP8 dense 2,614.9 TFLOPS
FP8 sparse 5,229.8 TFLOPS
FP4 dense —
FP4 sparse —
INT8 2,614.9 TOPS
Memory 256 GB HBM3E
Memory bandwidth 6,000 GB/s
Interconnect bandwidth —
Thermal design power 1,000 W
Process node TSMC 5nm/6nm
Architecture CDNA3
Compliance variant of —
Total Processing Performance 20,919.2 (FP8 × bit-length; ≈4.36× the 3A090.a parameter)
Regulatory basis January 2026 rule: case-by-case review for qualifying US exports to China or Macau.
Status source Conditions Subject to the same aggregate-TPP cap and additional application requirements as H200; see the cited rule.
Source Primary source AMD Instinct MI325X data sheet — open
Notes MI325X retains the MI300X compute architecture with 256 GB HBM3E at 6,000 GB/s and 1,000 W peak board power. The AMD datasheet lists 2,614.9 dense FP8 TFLOPS and 5,229.8 with sparsity. Earlier versions of this entry repeated MI300X FP8 values; the current figures follow the MI325X datasheet.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Country access Covered in 3 of the 26 country access profiles — 2 available (United States, United Kingdom) , 1 case-by-case (China) ; see country access profiles .
MI350X FP16 dense 2,309.6 TFLOPS
FP16 sparse 4,619.2 TFLOPS
BF16 dense 2,309.6 TFLOPS
TF32 dense —
TF32 sparse —
FP8 dense 4,614 TFLOPS
FP8 sparse 9,227.4 TFLOPS
FP4 dense 9,227.5 TFLOPS
FP4 sparse —
INT8 4,614 TOPS
Memory 288 GB HBM3E
Memory bandwidth 8,000 GB/s
Interconnect bandwidth —
Thermal design power 1,000 W
Process node TSMC N3P + N6
Architecture CDNA 4
Compliance variant of —
Total Processing Performance 36,953.6 (FP16 × bit-length; ≈7.7× the 3A090.a parameter)
Regulatory basis At 8,000 GB/s, memory bandwidth exceeds the 6,500 GB/s ceiling for conditional case-by-case review of US exports to China or Macau under the January 2026 rule.
Status source Source Primary source AMD MI350X GPU brochure (CDNA 4, Advancing AI 2025) — published June 2025 — open
Notes Air-cooled CDNA 4 GPU rated at 1,000 W peak board power, with 288 GB HBM3E at 8 TB/s. AMD’s brochure lists 4.614 dense OCP-FP8 PFLOPS and 9.2274 with sparsity; MXFP4 is 9.2275 dense PFLOPS. Earlier versions of this entry mistook sparse figures for dense performance. The table follows the brochure’s dense column.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Ascend 910B FP16 dense ~ 375 TFLOPS
FP16 sparse —
BF16 dense ~ 375 TFLOPS
TF32 dense —
TF32 sparse —
FP8 dense —
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 ~ 750 TOPS
Memory ~ 64 GB
Memory bandwidth ~ 1,600 GB/s
Interconnect bandwidth —
Thermal design power ~ 310 W
Process node SMIC N+2 (~7nm class, 2nd-gen)
Architecture Da Vinci
Compliance variant of —
Total Processing Performance ~ 6,000 (FP16 × bit-length; ≈1.25× the 3A090.a parameter)
Regulatory basis Named in BIS’s May 2025 guidance on chips presumptively subject to General Prohibition 10.
Status source Source Research database CSET Georgetown "Pushing the Limits" sub-variant analysis (Scrutica's own cited tier-2 source) — open
Notes This entry represents the Ascend 910B2 variant in CSET’s Pushing the Limits, Appendix Table 2: 375 FP16 TFLOPS, 64 GB memory and 1,600 GB/s bandwidth. Other 910B variants range from 280 to 400 FP16 TFLOPS. Epoch AI lists 376 for its base 910B entry. Power estimates vary across sources, including 310–350 W and Epoch’s 400 W. The older Ascend 910A’s 256 TFLOPS figure does not describe this variant.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Gaudi 2 FP16 dense —
FP16 sparse —
BF16 dense —
TF32 dense —
TF32 sparse —
FP8 dense —
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 —
Memory ~ 96 GB
Memory bandwidth ~ 2,450 GB/s
Interconnect bandwidth —
Thermal design power ~ 600 W
Process node TSMC 7nm
Architecture Gaudi
Compliance variant of —
Total Processing Performance Insufficient published specifications
Regulatory basis Exceeds performance thresholds. Subject to standard ECCN 3A090 controls.
Source Research database Intel developer documentation; Anandtech (archived) — open
Notes The approximate 600 W power figure is inferred from reporting that Gaudi 3’s 900 W is 50% higher. No comparable dense FP16/BF16 throughput is held here. Memory and interconnect figures come from Intel documentation. The interconnect uses Ethernet RoCE2.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Gaudi 3 FP16 dense —
FP16 sparse —
BF16 dense 1,835 TFLOPS
TF32 dense —
TF32 sparse —
FP8 dense 1,835 TFLOPS
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 —
Memory 128 GB HBM2e
Memory bandwidth 3,700 GB/s
Interconnect bandwidth —
Thermal design power 900 W
Process node TSMC 5nm
Architecture Gaudi
Compliance variant of —
Total Processing Performance 29,360 (BF16 × bit-length; ≈6.12× the 3A090.a parameter)
Regulatory basis Exceeds performance thresholds. Subject to standard ECCN 3A090 controls.
Source Primary source Intel Gaudi 3 datasheet (cdrdv2-public.intel.com/845118) — open
Notes Specifications apply to the OAM HL-325L variant at 900 W; the PCIe HL-338 is rated at 600 W. Gaudi 3 uses Intel EMIB packaging and two TSMC N5 compute dies, with 24 Ethernet ports at 200 Gbps each. Intel lists 1,835 BF16 TFLOPS; Epoch AI lists 1,678. This table uses Intel’s value. The reason for the difference has not been established here.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Google TPU v4 FP16 dense —
FP16 sparse —
BF16 dense 275 TFLOPS
TF32 dense —
TF32 sparse —
FP8 dense —
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 275 TOPS
Memory 32 GB HBM2
Memory bandwidth 1,200 GB/s
Interconnect bandwidth —
Thermal design power 170 W
Process node 7nm
Architecture TPU
Compliance variant of —
Total Processing Performance 4,400 (BF16 × bit-length; ≈0.917× the 3A090.a parameter)
Regulatory basis Offered through Google Cloud TPU. The cited product documentation does not establish its China export classification.
Source Primary source Google Cloud TPU v4 documentation — open
Notes Google documents 275 BF16 TFLOPS per chip and 32 GiB HBM2 at 1,200 GB/s. The 170 W figure is mean measured power in the ISCA 2023 paper (90 W minimum, 192 W maximum), rather than a thermal design rating. Each chip has two TensorCores with four matrix-multiply units apiece.
Recorded deployments This accelerator appears at 1 of the 9 facilities with GPU inventories: Google Oklahoma TPU v4 Pods — 32,768 × Google TPU v4
TPU v5e FP16 dense —
FP16 sparse —
BF16 dense 197 TFLOPS
TF32 dense —
TF32 sparse —
FP8 dense —
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 393 TOPS
Memory 16 GB HBM2e
Memory bandwidth 819 GB/s
Interconnect bandwidth —
Thermal design power —
Process node —
Architecture TPU
Compliance variant of —
Total Processing Performance 3,152 (BF16 × bit-length; ≈0.657× the 3A090.a parameter)
Regulatory basis Offered through Google Cloud TPU. The cited product documentation does not establish its China export classification.
Source Primary source Google Cloud TPU v5e documentation — open
Notes Google documents 197 BF16 TFLOPS, 393 INT8 TOPS, 16 GB HBM2e and 819 GB/s memory bandwidth. The chip has one TensorCore with a 128×128 matrix-multiply unit. Different precision formats and instruction sets limit direct performance comparisons with NVIDIA and AMD GPUs.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Google TPU v5p FP16 dense —
FP16 sparse —
BF16 dense 459 TFLOPS
TF32 dense —
TF32 sparse —
FP8 dense 459 TFLOPS
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 918 TOPS
Memory 95 GB HBM2e
Memory bandwidth 2,575 GB/s
Interconnect bandwidth 1,200 GB/s
Thermal design power —
Process node —
Architecture TPU
Compliance variant of —
Total Processing Performance 7,344 (BF16 × bit-length; ≈1.53× the 3A090.a parameter)
Regulatory basis Offered through Google Cloud TPU. The cited product documentation does not establish its China export classification.
Source Primary source Google Cloud TPU v5p documentation — open
Notes Google documents 459 BF16 TFLOPS, 95 GiB HBM and 2,575 GB/s memory bandwidth per chip, with 1,200 GB/s bidirectional ICI. Each chip has two TensorCores and four SparseCores. The INT8 value in this dataset is derived at twice BF16 throughput; Google does not separately publish it in the cited specification.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Google TPU v6e (Trillium) FP16 dense —
FP16 sparse —
BF16 dense 918 TFLOPS
TF32 dense —
TF32 sparse —
FP8 dense —
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 1,836 TOPS
Memory 32 GB HBM
Memory bandwidth 1,638 GB/s
Interconnect bandwidth 800 GB/s
Thermal design power —
Process node —
Architecture Trillium
Compliance variant of —
Total Processing Performance 14,688 (BF16 × bit-length; ≈3.06× the 3A090.a parameter)
Regulatory basis Offered through Google Cloud TPU. The cited product documentation does not establish its China export classification.
Source Primary source Google Cloud TPU v6e documentation — open
Notes 918 TFLOPS BF16 and 1,836 TOPS INT8 per chip per Google Cloud docs; 32 GB HBM at 1,638 GiB/s; ICI 800 GB/s per chip bidirectional. 256-chip pod = 234.9 PFLOPS BF16, 102.4 TB/s all-reduce. Announced May 2024; public-cloud preview Oct 2024. Optimized for transformer, text-to-image, and CNN training/serving.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
NVIDIA B300 FP16 dense —
FP16 sparse —
BF16 dense —
TF32 dense —
TF32 sparse —
FP8 dense 5,000 TFLOPS
FP8 sparse 10,000 TFLOPS
FP4 dense 15,000 TFLOPS
FP4 sparse 20,000 TFLOPS
INT8 —
Memory 288 GB HBM3E
Memory bandwidth 8,000 GB/s
Interconnect bandwidth —
Thermal design power 1,400 W
Process node TSMC N4
Architecture Blackwell Ultra
Compliance variant of —
Total Processing Performance 60,000 (FP4 × bit-length; ≈12.5× the 3A090.a parameter)
Regulatory basis Exceeds all BIS advanced computing thresholds (ECCN 3A090/4A090)
Source Primary source NVIDIA Technical Blog "Inside NVIDIA Blackwell Ultra" + GB300 NVL72 product page — open
Notes NVIDIA reports 15 dense and 20 sparse NVFP4 PFLOPS per chip, alongside 5 dense and 10 sparse FP8 PFLOPS. The FP4 sparse-to-dense ratio is therefore 1.33×; applying the usual 2× multiplier would overstate sparse throughput. B300 increases dense FP4 throughput as well as memory capacity relative to B200.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Country access Covered in 3 of the 26 country access profiles — 1 available (United Arab Emirates) , 1 case-by-case (Saudi Arabia) , 1 restricted (China) ; see country access profiles .
AMD Instinct MI355X FP16 dense 2,516.6 TFLOPS
FP16 sparse 5,033.2 TFLOPS
BF16 dense 2,516.6 TFLOPS
TF32 dense —
TF32 sparse —
FP8 dense 5,033.2 TFLOPS
FP8 sparse 10,066.4 TFLOPS
FP4 dense 10,066.3 TFLOPS
FP4 sparse —
INT8 5,033.2 TOPS
Memory 288 GB HBM3E
Memory bandwidth 8,000 GB/s
Interconnect bandwidth —
Thermal design power 1,400 W
Process node TSMC N3P + N6
Architecture CDNA 4
Compliance variant of —
Total Processing Performance 40,265.6 (FP16 × bit-length; ≈8.39× the 3A090.a parameter)
Regulatory basis Exceeds BIS advanced computing thresholds
Source Primary source AMD MI355X GPU brochure (CDNA 4, Advancing AI 2025) — open
Notes Liquid-cooled CDNA 4 GPU rated at 1,400 W peak board power, with 288 GB HBM3E at 8 TB/s. AMD’s brochure lists 5.0332 dense OCP-FP8 PFLOPS and 10.0664 with sparsity; MXFP4 is 10.0663 dense PFLOPS. Earlier versions of this entry used sparse or launch-slide figures in dense fields. Epoch AI lists 4.6 FP8 PFLOPS; the table follows AMD’s brochure.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
AMD Instinct MI400 FP16 dense —
FP16 sparse —
BF16 dense —
TF32 dense —
TF32 sparse —
FP8 dense ~ 20,000 TFLOPS
FP8 sparse —
FP4 dense ~ 40,000 TFLOPS
FP4 sparse —
INT8 —
Memory ~ 432 GB
Memory bandwidth ~ 19,600 GB/s
Interconnect bandwidth —
Thermal design power —
Process node —
Architecture CDNA 5
Compliance variant of —
Total Processing Performance ~ 160,000 (FP8 × bit-length; ≈33.3× the 3A090.a parameter)
Regulatory basis The announced 19,600 GB/s memory bandwidth exceeds the 6,500 GB/s ceiling for conditional case-by-case review of US exports to China or Macau under the January 2026 rule.
Status source Source Primary source AMD Advancing AI Event June 2025 — open
Notes AMD’s June 2025 announcement described a 72-GPU Helios rack with 260 TB/s scale-up bandwidth and Ultra Accelerator Link. The announcement targeted 2026 availability; the figures here are estimates from that announcement.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Google TPU v7 (Ironwood) FP16 dense —
FP16 sparse —
BF16 dense —
TF32 dense —
TF32 sparse —
FP8 dense 4,614 TFLOPS
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 —
Memory 192 GB HBM3E
Memory bandwidth 7,370 GB/s
Interconnect bandwidth —
Thermal design power —
Process node —
Architecture Ironwood
Compliance variant of —
Total Processing Performance 36,912 (FP8 × bit-length; ≈7.69× the 3A090.a parameter)
Regulatory basis Offered through Google Cloud. The cited product announcement does not establish its China export classification.
Source Primary source Google Cloud blog (Ironwood: the age of inference) — open
Notes Google’s announcement describes a pod of 9,216 chips with 42.5 exaFLOPS FP8 throughput. Per-chip wattage is not given in the cited announcement. A previously recorded 960 W figure was removed because it lacked source support.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
AWS Trainium3 FP16 dense —
FP16 sparse —
BF16 dense —
TF32 dense —
TF32 sparse —
FP8 dense ~ 2,520 TFLOPS
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 —
Memory ~ 144 GB
Memory bandwidth ~ 4,900 GB/s
Interconnect bandwidth —
Thermal design power —
Process node TSMC N3
Architecture Trainium
Compliance variant of —
Total Processing Performance ~ 20,160 (FP8 × bit-length; ≈4.2× the 3A090.a parameter)
Regulatory basis Offered through AWS EC2. The cited product announcement does not establish its China export classification.
Source Primary source AWS Trn3 UltraServer announcement — open
Notes AWS announced general availability of EC2 Trn3 UltraServers in December 2025, with up to 144 chips per system. The announcement publishes compute, memory and bandwidth specifications but no per-chip wattage. Power is left unavailable.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Cerebras WSE-3 FP16 dense —
FP16 sparse —
BF16 dense —
TF32 dense —
TF32 sparse —
FP8 dense —
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 —
Memory 44 GB On-chip SRAM
Memory bandwidth 21,000,000 GB/s
Interconnect bandwidth —
Thermal design power —
Process node TSMC 5nm
Architecture Wafer-scale
Compliance variant of —
Total Processing Performance Insufficient published specifications
Regulatory basis The cited specifications do not establish its China export classification. No verified dense throughput is available here for a numerical TPP comparison.
Source Primary source Cerebras WSE-3 announcement; FP16 headline from Cerebras CS-3/B200 comparison (https://www.cerebras.ai/blog/cerebras-cs-3-vs-nvidia-b200-2024-ai-accelerators-compared) — open
Notes Cerebras advertises 125 PFLOPS at FP16 in its CS-3/B200 comparison, but does not specify a dense basis or separate BF16 throughput. Those fields remain unavailable here. Its 21 PB/s bandwidth describes on-wafer SRAM traffic, excluded from comparisons with off-die GPU memory bandwidth. WSE-3 has 4 trillion transistors and 900,000 AI cores.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Tenstorrent Wormhole n300 FP16 dense 131 TFLOPS
FP16 sparse —
BF16 dense —
TF32 dense —
TF32 sparse —
FP8 dense 466 TFLOPS
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 —
Memory 24 GB GDDR6
Memory bandwidth 576 GB/s
Interconnect bandwidth —
Thermal design power —
Process node —
Architecture Wormhole (Tensix)
Specification scope Two-chip board
Compliance variant of —
Total Processing Performance Insufficient published specifications
Regulatory basis The cited hardware specifications do not establish its China export classification. The n300 figures describe a two-ASIC board; ECCN 3A090 evaluates performance per integrated circuit.
Source Primary source Tenstorrent Wormhole specifications (docs.tenstorrent.com) — open
Notes Two-ASIC board with 128 Tensix cores (64 per ASIC) at 1 GHz. All listed compute, memory and bandwidth figures describe the board: 131 TFLOPS FP16, 466 TFLOPS FP8, 262 TFLOPS BFP8, 24 GB GDDR6 and 576 GB/s. Published total board power is 300 W; chip TDP is unavailable. These board aggregates are excluded from per-chip rankings and TPP calculations.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Tenstorrent Blackhole p150 FP16 dense —
FP16 sparse —
BF16 dense —
TF32 dense —
TF32 sparse —
FP8 dense 664 TFLOPS
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 —
Memory 32 GB GDDR6
Memory bandwidth 512 GB/s
Interconnect bandwidth —
Thermal design power 300 W
Process node —
Architecture Blackhole (Tensix Gen2)
Compliance variant of —
Total Processing Performance 5,312 (FP8 × bit-length; ≈1.11× the 3A090.a parameter)
Regulatory basis The cited hardware specifications do not establish its China export classification. Its published 664 TFLOPS BLOCKFP8 yields 5,312 under this tool’s TPP calculation, above the 4,800 numerical threshold; this comparison is not a licensing determination.
Source Primary source Tenstorrent Blackhole specifications — open
Notes 120 Tensix cores (Gen2), 16 RISC-V big cores, 1.35 GHz AI clock. 664 TFLOPS BLOCKFP8 per chip; 32 GB GDDR6 at 512 GB/s. 4× QSFP-DD 800 G Ethernet for scale-out. FP16/BF16 peak not separately published by Tenstorrent. Released 2025. Companion p100a variant: 28 GB GDDR6 / 448 GB/s / no QSFP-DD; p150b: same as p150a with regional SKU difference.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Huawei Ascend 910C FP16 dense —
FP16 sparse —
BF16 dense ~ 780 TFLOPS
TF32 dense —
TF32 sparse —
FP8 dense —
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 —
Memory ~ 128 GB
Memory bandwidth ~ 3,200 GB/s
Interconnect bandwidth —
Thermal design power ~ 700 W
Process node SMIC N+2 (~7nm class, 2nd-gen)
Architecture Da Vinci
Compliance variant of —
Total Processing Performance ~ 12,480 (BF16 × bit-length; ≈2.6× the 3A090.a parameter)
Regulatory basis Named in BIS’s May 2025 guidance on chips presumptively subject to General Prohibition 10.
Status source Source Research database DeepSeek research / Tom's Hardware — open
Notes The cited reporting attributes the compute chiplet to SMIC N+2. Reported BF16 throughput differs: this dataset holds 780 TFLOPS, while Epoch AI lists 800. CloudMatrix 384 is reported at 300 BF16 PFLOPS across 384 chips. Specifications remain estimates; the source of the per-chip discrepancy is not established here.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Huawei Ascend 910D FP16 dense —
FP16 sparse —
BF16 dense —
TF32 dense —
TF32 sparse —
FP8 dense —
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 —
Memory —
Memory bandwidth —
Interconnect bandwidth —
Thermal design power —
Process node 5nm
Architecture Da Vinci
Compliance variant of —
Total Processing Performance Insufficient published specifications
Regulatory basis Named in BIS’s May 2025 guidance on chips presumptively subject to General Prohibition 10.
Status source Source Press or analyst Tom's Hardware — open
Notes Reporting described customer trials in April–May 2025 and projected mass production for Q2–Q3 2026. FP8 support and HCCS 4.0 interconnect were reported, but no numerical compute or memory-bandwidth specification is held here. The production projection has not been verified as an outcome.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
Huawei Ascend 920 FP16 dense —
FP16 sparse —
BF16 dense ~ 900 TFLOPS
TF32 dense —
TF32 sparse —
FP8 dense —
FP8 sparse —
FP4 dense —
FP4 sparse —
INT8 —
Memory —
Memory bandwidth ~ 4,000 GB/s
Interconnect bandwidth —
Thermal design power —
Process node SMIC N+3 (6nm-class)
Architecture Da Vinci
Compliance variant of —
Total Processing Performance ~ 14,400 (BF16 × bit-length; ≈3× the 3A090.a parameter)
Regulatory basis Chinese-designed accelerator. The cited reporting does not establish whether particular items or transactions are subject to the EAR.
Source Research database TrendForce — open
Notes TrendForce’s April 2025 report projected a second-half 2025 launch as an alternative to H20. Specifications here are estimates from that reporting; the projected launch date is not confirmation of availability.
Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities.
NVIDIA Ampere A800 reduced A100 interconnect bandwidth while retaining its compute throughput. The October 2023 revision removed interconnect bandwidth as a control parameter and restricted A800.
Models A100 SXM
A800
NVIDIA Hopper H800 reduced interconnect bandwidth; H20 instead reduced compute while retaining substantial memory and interconnect bandwidth. The policy history includes restrictions on H800, a separate H20 licensing requirement and conditional case-by-case review for H200. Model details distinguish these actions and their dates.
Models H100 SXM5
H100 PCIe
H100 NVL
H800 SXM5
H800 PCIe
H200 SXM
H20 SXM
H20E (HBM3E refresh)
NVIDIA Blackwell B100 and B200 differ in power and throughput. B300 Blackwell Ultra raises dense FP4 throughput and memory capacity; B30A was reported as a proposed single-die variant for China, with specifications that remain estimates.
Models B100
B200
NVIDIA B300
B30A
NVIDIA Rubin Rubin GPU preliminary individual-GPU specifications: 35 PFLOPS dense NVFP4 training, 17.5 PFLOPS dense FP8/FP6 training, 4 PFLOPS dense FP16/BF16, 288 GB HBM4 at 22 TB/s, and 3.6 TB/s NVLink. NVIDIA marks the figures as up to and subject to change.
Models NVIDIA Rubin GPU
AMD Instinct MI325X expands memory relative to MI300X. The CDNA 4 MI350X and MI355X differ in cooling and throughput: MI350X is air-cooled, MI355X liquid-cooled. Their datasheets distinguish dense from sparse performance; the table uses dense values. MI400 specifications remain estimates from AMD’s June 2025 announcement.
Models MI300X
MI325X
MI350X
AMD Instinct MI355X
AMD Instinct MI400
Huawei Ascend The 910B entry represents CSET’s 910B2 variant. The 910C estimate differs from Epoch AI’s reported throughput; 910D lacks numerical compute specifications here. The cited 920 report describes a projected launch. These differences in evidence limit comparisons across the family.
Models Ascend 910B
Huawei Ascend 910C
Huawei Ascend 910D
Huawei Ascend 920
Intel Gaudi Gaudi 2 and Gaudi 3 use Ethernet interconnects. Gaudi 3 combines TSMC N5 compute dies with Intel EMIB packaging. Its OAM and PCIe variants have different power ratings; this table represents the OAM variant.
Models Gaudi 2
Gaudi 3
AWS Trainium Trainium3 powers EC2 Trn3 UltraServers, which AWS announced as generally available in December 2025. Access is offered through AWS services. Per-chip power is not supplied in the cited announcement.
Models AWS Trainium3
Cerebras Wafer-Scale Engine WSE-3 uses wafer-scale integration and on-wafer SRAM. Its wafer-wide compute and bandwidth figures require separate treatment from per-GPU specifications.
Models Cerebras WSE-3
Tenstorrent Wormhole n300 is a dual-ASIC PCIe card. Blackhole p150 uses the second-generation Tensix architecture with Ethernet scale-out. Its published compute figure uses BLOCKFP8; no dense FP16/BF16 figure is held here.
Models Tenstorrent Wormhole n300
Tenstorrent Blackhole p150
October 2022 Advanced Computing Rule Effective 21 Oct 2022
That day brought in ECCNs 3A090 and 4A090 (advanced computing ICs and computers) and the revised § 744.23. Other provisions of the rule took effect on 7 Oct 2022 and 12 Oct 2022; its entry on Regimes lists each stage.
Compute performance (TFLOPS) and interconnect bandwidth
ECCN 3A090 combined an aggregate bidirectional transfer rate of at least 600 GB/s to or from other ICs, excluding volatile memories, with compute criteria equivalent to at least 4,800 bits × TOPS. Both bandwidth and compute conditions had to be met.
Oct 2022 interconnect threshold (600 GB/s): 600 GB/s
87 FR 62186
87 FR 62186
Newly restricted A100 SXM
H100 SXM5
October 2023 Advanced Computing Update Effective 17 Nov 2023
Total Processing Performance (TPP): 2 × MacTOPS × bit-length, summed across processing units
Introduced the TPP metric — dense throughput × bit-length of the operation, evaluated at the highest value across supported bit-lengths, dense matrices only. Also broadened end-use controls. 3A090.a also has a second leg (TPP ≥ 1,600 with performance density ≥ 5.92) that requires applicable die area, which no record here publishes.
ECCN 3A090.a: 4,800 TPP (2 × MacTOPS × bit-length; verified against 88 FR 73458 and the current CCL)
88 FR 73458
88 FR 73458
Newly restricted A800
H800 SXM5
H800 PCIe
December 2024 Expansion Effective 2 Dec 2024
HBM memory bandwidth density
Added ECCN 3A090.c for HBM above 2 GB/s/mm² of memory bandwidth density, calculated from package or stack bandwidth and area. Certain co-packaged HBM-and-logic ICs whose dominant function is processing are excluded. The rule took effect December 2; compliance with the HBM provisions began December 31, 2024.
89 FR 96790
89 FR 96790
Newly restricted No newly restricted chips are recorded here for this action.
April 2025 H20 License Requirement Effective 9 Apr 2025
No new threshold metric. License-required determination on the previously-compliant-by-design H20.
NVIDIA reported an April 9 government notice requiring licenses for H20 and other ICs meeting specified H20 bandwidth characteristics. It covered exports to China, including Hong Kong and Macau, D:5 countries, and companies headquartered or with an ultimate parent there. NVIDIA disclosed the notice on April 15.
NVIDIA Form 8-K, filed April 15, 2025; reports April 9 government notice
NVIDIA Form 8-K
Newly restricted H20 SXM
July 2025 H20 Licensing Announcement Effective 14 Jul 2025
Announcement of expected licensing; no technical threshold change.
NVIDIA announced assurances that licenses would be granted. Its August 2025 filing later confirmed licenses for selected H20 customers, and described a 15% revenue-share expectation from U.S. officials with no codifying regulation at that time.
NVIDIA announcement (July 14, 2025); NVIDIA August 2025 Form 10-Q
NVIDIA announcement
NVIDIA August 2025 filing
Newly restricted No newly restricted chips are recorded here for this action.
January 2026 License Review Policy Revision Effective 15 Jan 2026
TPP below 21,000 and total DRAM bandwidth below 6,500 GB/s: the ceilings for conditional case-by-case review.
Provides case-by-case review for qualifying US exports to China or Macau below 21,000 TPP and 6,500 GB/s total DRAM bandwidth. H200 and MI325X are examples. Approval depends on the rule’s supply, aggregate-TPP, end-use, security and testing conditions.
91 FR 1684
91 FR 1684
Newly restricted No newly restricted chips are recorded here for this action.
2 corrections▾ Sources 12 of 35 accelerators have estimated specifications. Each chip lists its specification source and the stated basis for its China export status; the vendor rows above count each vendor's chips and link the source most of them cite. Policy history in this dataset runs through January 2026 .
9 sources Data How the figures were made How a chip is classified. Under the October 2023 Advanced Computing Update, TPP is 2 × MacTOPS × bit-length, summed across processing units (88 FR 73458). For dense FP16, this is 16 times the published TFLOPS. The calculation uses the highest TPP available across each chip’s published bit-lengths, and each result is compared with the ECCN 3A090.a threshold of 4,800. Licensing also depends on the transaction and the other applicable controls.
9 of the 35 accelerators have no dense FP16/BF16 specification in this dataset; other published precisions can still support a TPP calculation. TPP cannot be evaluated for 4 chips, which publish no dense per-IC figure.
6 accelerators are offered through Google Cloud or AWS, and the cited product documentation classifies none of them for China export. 4 have a dense-FP16/BF16-based TPP above the H20 SXM’s 2,368, the lowest such reading among chips newly restricted by the actions listed here.
The threshold strip. TPP uses dense throughput at each chip’s highest published basis under ECCN 3A090 (88 FR 73458); the default threshold is 4,800. Board totals and peaks without a verified dense basis are excluded. TPP could not be calculated for Gaudi 2, Cerebras WSE-3, Tenstorrent Wormhole n300, Huawei Ascend 910D from the available specifications. ECCN 3A090.a.2 also covers TPP ≥ 1,600 with performance density ≥ 5.92. This calculation requires applicable die area, which is unavailable in this dataset. Chips below 4,800 TPP may therefore still meet that criterion.
For restrictions on semiconductor manufacturing equipment, see supply-chain chokepoints .