Compute verification
Each entry identifies the relevant provisions or sections.
II.16 the covered cluster; V.1–6 consolidation, the register, transfers; VII.1–5 use verification; X.3–4 challenge inspections and disclosure; Appendix C staging
a chip registry, sampled physical inventory checks, movement monitoring, hardware-key concerns (pp. 14–16)
the six layers; A.4 partial re-execution with constraints; A.6 compute accounting via analog sensors; §4.3 personnel-based layers; B.2 narrower rules; B.3 precautionary pauses
§2.5.3 verifiable confidential computing; §3.6.1 neutral mutually verified data centre
the whole report; the About This Report section states its scope
guarantee processor and secure enclosure (p. 3); the interlock on the data path (p. 23); retrofit options (pp. 9, 24)
Verification-based and ruleset-based agreements (pp. 36–38)
evidence capture and commitment separated from evaluation; physical security as a prerequisite (p. 2)
§2.3 the classification task; §§4–5 results; Appendix F limits
Distributed training and compute governance; the simulator (§5.4)
the two-node setup; DiLoCo; the limitations on reinforcement learning and LoRA
§1.2 inventory against shipments, printed serials, powered-on attestation; §3.2 the compute formula
the landmark server and the round-trip delay bound
Location verification through timed exchanges
§3.3.3 compute accounting
the technical annex: random selection from the registry and short-notice inspection
A taxonomy of verification methods, including remote sensing
§3.1 the inspection; §3.2 how many chips; Appendix B the sampling model
the abstract: disaggregated architectures decouple rollout generation and policy training across independent GPU pools
IX.16–17, 21 challenge inspections; Part X paras 45–48 managed access
Attestation claims for hardware model, device identity, driver and vBIOS reference measurements, secure boot and debug state
H100-equivalent capacity definition and catalogue coverage
