Method 2026-09-05
Compute Leverage
Leverage over a frontier training run, measured as switching cost times redeployment time.
Leverage over a frontier training run, measured as switching cost times redeployment time.
Pinned viewThe assessments below use Anthropic’s training setup. Return to the baseline.
| Leverage point | 18 months | 5 years |
|---|---|---|
| EDA tools (chip design) | Can gate a run | Can gate a run |
| EUV lithography | Can gate a run | Can gate a run |
| Advanced logic foundry (≤5nm/3nm) | Can gate a run | Uncertain |
| Advanced packaging / CoWoS | Can gate a run | Uncertain |
| HBM memory (HBM3E / HBM4) | Can gate a run | Cannot gate |
| Capital ($1B+/yr runs) | Uncertain | Cannot gate |
| Cloud / datacenter capacity | Uncertain | Cannot gate |
| Power / grid interconnection | Cannot gate | Uncertain |
| AI accelerator | Cannot gate | Cannot gate |
| Scale-out interconnect (InfiniBand vs Ethernet) | Cannot gate | Cannot gate |
| Scale-up interconnect (NVLink / NVSwitch) | Cannot gate | Cannot gate |
Each line follows one leverage point across two assessments: could its holder delay a new training run beyond eighteen months, and could it still do so if the lab had five years to find an alternative?
Line weight indicates the source quality of the time needed to switch suppliers or infrastructure: solid for primary sources or research, lighter for press or analyst estimates, dotted where no source was found.
A hollow square marks a gate held by several institutions acting together. The assessments use Anthropic’s training setup. The comparison below includes the other two labs and the baseline.
The five-year assessments depend on judgements about future alternatives: two of the five points that can delay a run at eighteen months are uncertain at five years.
The assessment covers eleven points where a supplier or institution could prevent a lab from starting a new training run. Five can do so over an eighteen-month horizon; two remain barriers at five years: EDA tools (chip design) and EUV lithography. Each of the five has an identified institutional or market constraint. Export controls apply to all five and restrict whom the holder may supply; they do not give a lab an entitlement to buy. These counts concern access to a new run. They do not measure the power to interrupt training already under way.
Anthropic’s run · Eighteen-month assessment
The symbols show whether each leverage point could delay the selected run beyond eighteen months: solid for yes, hollow for no, diamond for uncertain. Bands appear beside yes verdicts and distinguish the ability to refuse supply from the ability to decide who receives it. A shipment restriction gives no buyer a place in the queue.
Scrutica assigns these powers by the kind of institution or rule listed in the register. The bands describe that general assessment; the cited sources do not establish that each mechanism can direct supply to the selected lab.
| Leverage point | 18 months | 5 years | Checked by | Redeployment time |
|---|---|---|---|---|
| EUV lithography · ASML | can gate | can gate | Export control — A sole-supplier monopoly over EUV scanners, governed by Dutch + US multilateral export-control law: a state has asserted jurisdiction over whom ASML may sell to, and no second supplier exists to check it commercially. | No commercial alternative at any horizon for a Western lab; state-built EUV at scale assessed 5-10+ years out · estimated |
| Advanced logic foundry (≤5nm/3nm) · TSMC, Samsung Foundry, Intel Foundry | can gate | uncertain | Export control — Leading-edge logic fabrication is governed by US export-control law: the Foreign Direct Product Rule reaches any chip made with US tooling, and the Jan-2025 Foundry Due-Diligence Rule mandates quarterly OSAT/foundry KYC compliance reporting to BIS. | No published figure for a full TSMC→Samsung inter-foundry port of a leading-edge AI accelerator · no source found |
| EDA tools (chip design) · Synopsys, Cadence, Siemens EDA | can gate | can gate | Export control — EDA for leading-edge design is governed by US export-control law: BIS exercised a standing enforcement order (Cadence $95M penalty, 28 Jul 2025, for EDA exports to Entity-List parties NUDT/Phytium under EAR §744). The broader China-sales licensing letters to Synopsys/Cadence/Siemens (imposed 23 May 2025) were rescinded 2 Jul 2025 under the US–China framework, so the enforcement order is what remains in force, and the letters are rescinded. | No production leading-edge alternative at any horizon; a full design re-verification on a second toolchain has no qualified ≤7nm target. · no source found |
| HBM memory (HBM3E / HBM4) · SK Hynix, Samsung, Micron | can gate | cannot gate | Export control — HBM is governed by US export-control law — the Dec-2024 rule controls HBM at/above a bandwidth-density threshold (>2 GB/s/mm²), on top of the Oct-2022/Oct-2023 advanced-computing controls. | 12-24 months to qualify a secondary supplier, anchored to the Samsung→NVIDIA case (~18-month qualification for a supplier with a finished product) · estimated |
| Advanced packaging / CoWoS · TSMC, OSATs (ASE, Amkor, SPIL) | can gate | uncertain | Export control — Since 16 Jan 2025, with compliance required from 31 Jan, a BIS regime reaches the packaging layer directly: the Foundry Due-Diligence Rule (90 FR 5298, FR Doc. 2025-00711) makes approved-OSAT attestations the mechanism by which packaged advanced ICs escape licensing presumptions, keeps the approved-OSAT list at Supplement No. 7 to Part 740, and requires quarterly OSAT/foundry compliance reporting — the same rule already cited on the advanced-foundry layer, whose named obligors include this layer’s own holders. The Dec-2024 rule separately controls advanced-packaging equipment. | New OSAT production line ~6-9 months; customer-level requalification for a given accelerator unverified · no source found |
| AI accelerator · NVIDIA, Google TPU, AWS Trainium, AMD | cannot gate | cannot gate | Export control — Frontier AI accelerators are the primary object of US export-control law (ECCN 3A090/4A090; the Oct-2023 Total-Processing-Performance metric closed the A800/H800 work-arounds). | Committed labs (CUDA-bespoke): >18 months. Diversified/vertically-integrated labs: already routed around NVIDIA at production scale (not applicable). · estimated |
| Scale-up interconnect (NVLink / NVSwitch) · NVIDIA | cannot gate | cannot gate | Export control — Reached by the same US advanced-computing export-control architecture as the accelerator it binds: ECCN 3A090 has an I/O-bandwidth control parameter (≥150 GB/s aggregate bidirectional) and 4A090 covers electronic assemblies/components incorporating controlled accelerators (e.g. GB200 NVL72 racks). | No production UALink alternative until ~late 2026 at earliest (committed labs) · estimated |
| Scale-out interconnect (InfiniBand vs Ethernet) · NVIDIA/Mellanox InfiniBand, Broadcom/Arista Ethernet | cannot gate | cannot gate | Competition — Ethernet (Broadcom, Arista, Ultra Ethernet Consortium) is a production-scale alternative; demonstrated at frontier scale. | Routable to Ethernet now for a lab with fabric-engineering capacity · estimated |
| Cloud / datacenter capacity · AWS, Microsoft Azure, Google Cloud, CoreWeave, Oracle, neoclouds | uncertain | cannot gate | Competition — Capacity is fragmenting (97GW of new colocation projected 2025-30); multi-vendor structure means no single cloud provider is a unilateral veto for a top lab. | Binding for single-vendor-locked startups; not for multi-vendor pre-positioned labs · estimated |
| Power / grid interconnection · ISO/RTO (MISO, PJM, ERCOT, SPP), local utility, state PUC, FERC, EPA · institutions acting together | cannot gate | uncertain | Public body — The holders are public bodies, subject to democratic, regulatory and FOIA accountability, and the queue they run can order a connection as well as refuse one. | New site: ~4.5yr average to commercial operation (transformer ~160wk OR interconnection study alone exceeds 18 months). A well-capitalized lab can bypass the grid with on-site gas (the xAI Colossus route), so the new-site veto does not bind an incumbent already self-generating its power. · estimated |
| Capital ($1B+/yr runs) · hyperscaler balance sheets, sovereign funds (QIA, PIF, Mubadala), mega-VC | uncertain | cannot gate | Competition — Capital access is widening as sovereign funds and infrastructure investors enter, and the largest rounds are syndicated and partly compute-for-equity, so no one funder’s withdrawal halts a top lab. | No frontier-class lab was found single-funder-gated — the largest rounds are syndicates (Anthropic’s $30B Series G: 2 leads, 5 co-leads, ~30 named investors; OpenAI’s $122B round: 6 co-leads plus Amazon/NVIDIA/SoftBank/Microsoft). · estimated |
Needs verification Three redeployment-time coefficients have no published figure behind them: EDA tools (chip design), advanced logic foundry (≤5nm/3nm), advanced packaging / CoWoS. None of the three decides a verdict on its own, because the eighteen-month gate at each rests on capacity or on the absence of a qualified alternative, and both of those are sourced.
A gate binds a lab that cannot route around it, so the count is a property of the run as much as of the stack. Against the cross-run baseline of eight gates, a lab that designs its own accelerator and runs it on its own fabric clears the ones a CUDA-committed lab cannot.
A holder gates a run when switching cost × redeployment time exceeds the horizon, so the lab cannot route around it in time. Market share is carried as context and decides nothing: the scale-out interconnect layer is concentrated and gates nothing, because Ethernet is a substitute a lab can adopt now, while advanced packaging has no published share split and gates at eighteen months because capacity is allocated years out.
A can gate assessment means the lab cannot find an alternative within that time horizon. The five-year assessment allows more time to switch or build one. How leverage is derived
Scrutica assigns one accountability category to each layer, with export control taking priority over antitrust, a public body, competition and no identified constraint, in that order. The register gives the reason for each assignment.
A layer can be classified under competition and still delay a run if the lab cannot switch to the rival within eighteen months. Across the full register, 7 of 11 layers are classified under export control. What each kind of check can do, layer by layer.