Chip Classification

ReadingDense FP16/BF16 compute is in TFLOPS; memory bandwidth is in GB/s. Board and wafer-scale totals appear last, outside the per-chip throughput ordering.

1. 2022-10-21October 2022 Advanced Computing Rule87 FR 62186

   Compute performance (TFLOPS) and interconnect bandwidth

   ECCN 3A090 combined an aggregate bidirectional transfer rate of at least 600 GB/s to or from other ICs, excluding volatile memories, with compute criteria equivalent to at least 4,800 bits × TOPS. Both bandwidth and compute conditions had to be met.

   Oct 2022 interconnect threshold (600 GB/s) — 600 GB/s

   Newly restricted: A100 SXM, H100 SXM5.

2. 2023-11-17October 2023 Advanced Computing Update88 FR 73458

   Total Processing Performance (TPP): 2 × MacTOPS × bit-length, summed across processing units

   Introduced the TPP metric — dense throughput × bit-length of the operation, evaluated at the highest value across supported bit-lengths, dense matrices only. Closed the A800/H800 interconnect-reduction loophole. Also broadened end-use controls. 3A090.a also has a second leg (TPP ≥ 1,600 with performance density ≥ 5.92) that requires applicable die area, which no record here publishes.

   ECCN 3A090.a — 4,800 TPP (2 × MacTOPS × bit-length; verified against 88 FR 73458 and the current CCL)

   Newly restricted: A800, H800 SXM5, H800 PCIe.

3. 2024-12-02December 2024 Expansion89 FR 96790

   HBM memory bandwidth density

   Added ECCN 3A090.c for HBM above 2 GB/s/mm² of memory bandwidth density, calculated from package or stack bandwidth and area. Certain co-packaged HBM-and-logic ICs whose dominant function is processing are excluded. The rule took effect December 2; compliance with the HBM provisions began December 31, 2024.

   No newly restricted chips are recorded here for this action.

4. 2025-04-09April 2025 H20 License RequirementNVIDIA Form 8-K

   No new threshold metric. License-required determination on the previously-compliant-by-design H20.

   NVIDIA reported an April 9 government notice requiring licenses for H20 and other ICs meeting specified H20 bandwidth characteristics. It covered exports to China, including Hong Kong and Macau, D:5 countries, and companies headquartered or with an ultimate parent there. NVIDIA disclosed the notice on April 15.

   Newly restricted: H20 SXM.

5. 2025-07-14July 2025 H20 Licensing AnnouncementNVIDIA announcementNVIDIA August 2025 filing

   Announcement of expected licensing; no technical threshold change.

   NVIDIA announced assurances that licenses would be granted. Its August 2025 filing later confirmed licenses for selected H20 customers, and described a 15% revenue-share expectation from U.S. officials with no codifying regulation at that time.

   No newly restricted chips are recorded here for this action.

6. 2026-01-15January 2026 License Review Policy Revision91 FR 1684

   Conditional case-by-case licensing pathway for H200-class chips.

   Provides case-by-case review for qualifying US exports to China or Macau below 21,000 TPP and 6,500 GB/s total DRAM bandwidth. H200 and MI325X are examples. Approval depends on the rule’s supply, aggregate-TPP, end-use, security and testing conditions.

   No newly restricted chips are recorded here for this action.

NVIDIA Ampere NVIDIA

A800 reduced A100 interconnect bandwidth while retaining its compute throughput. The October 2023 revision removed interconnect bandwidth as a control parameter and restricted A800.

NVIDIA Hopper NVIDIA

H800 reduced interconnect bandwidth; H20 instead reduced compute while retaining substantial memory and interconnect bandwidth. The policy history includes restrictions on H800, a separate H20 licensing requirement and conditional case-by-case review for H200. Model details distinguish these actions and their dates.

NVIDIA Blackwell NVIDIA

B100 and B200 differ in power and throughput. B300 Blackwell Ultra raises dense FP4 throughput and memory capacity; B30A was reported as a proposed single-die variant for China, with specifications that remain estimates.

NVIDIA Rubin NVIDIA

Rubin GPU preliminary individual-GPU specifications: 35 PFLOPS dense NVFP4 training, 17.5 PFLOPS dense FP8/FP6 training, 4 PFLOPS dense FP16/BF16, 288 GB HBM4 at 22 TB/s, and 3.6 TB/s NVLink. NVIDIA marks the figures as up to and subject to change.

AMD Instinct AMD

MI325X expands memory relative to MI300X. The CDNA 4 MI350X and MI355X differ in cooling and throughput: MI350X is air-cooled, MI355X liquid-cooled. Their datasheets distinguish dense from sparse performance; the table uses dense values. MI400 specifications remain estimates from AMD’s June 2025 announcement.

Huawei Ascend Huawei

The 910B entry represents CSET’s 910B2 variant. The 910C estimate differs from Epoch AI’s reported throughput; 910D lacks numerical compute specifications here. The cited 920 report describes a projected launch. These differences in evidence limit comparisons across the family.

Intel Gaudi Intel

Gaudi 2 and Gaudi 3 use Ethernet interconnects. Gaudi 3 combines TSMC N5 compute dies with Intel EMIB packaging. Its OAM and PCIe variants have different power ratings; this table represents the OAM variant.

Google TPU Google

TPU v5e targets efficiency; v5p expands memory and interconnect bandwidth for training. Trillium and Ironwood increase compute throughput, with Ironwood reported at FP8. TPU v4’s recorded power is a measured mean; per-chip power is unavailable here for Ironwood.

AWS Trainium Amazon

Trainium3 powers EC2 Trn3 UltraServers, which AWS announced as generally available in December 2025. Access is offered through AWS services. Per-chip power is not supplied in the cited announcement.

Cerebras Wafer-Scale Engine Cerebras

WSE-3 uses wafer-scale integration and on-wafer SRAM. Its wafer-wide compute and bandwidth figures require separate treatment from per-GPU specifications.

Tenstorrent Tenstorrent

Wormhole n300 is a dual-ASIC PCIe card. Blackhole p150 uses the second-generation Tensix architecture with Ethernet scale-out. Its published compute figure uses BLOCKFP8; no dense FP16/BF16 figure is held here.