Checked 2026-08-13 · unchanged since 2025-11-10RSS

Export Controls

The restrictions in force, the entities they name, and their measured effect on trade.

19 of 36 tracked accelerators are restricted for China

Every AI accelerator placed against the control thresholds: EAR classification (ECCN 3A090/4A090), performance parameters, and license-exception applicability per destination.

Restricted for China: no licence pathway under the rules in force.

Licence required, reviewed case by case, with conditions attached.

Engineered to fall below the thresholds. The one such part publishes no figure on either axis, so the compliance category is exactly where the specifications go dark.

Chinese-manufactured, outside US export control directly — though their fabricators inherit equipment restrictions.

Outside the controls: internal cloud silicon that is never sold, or parts below the classification threshold.

Carry estimated specifications, drawn with a dashed stroke. Huawei publishes no Ascend datasheet, and the China-channel NVIDIA parts have none either.

Threshold rules on record, 2022–2026, drawn on the date rail beneath the field. One carries a quantitative value — 600 GB/s of aggregate interconnect — measured on an axis this field does not plot. 3 parts publish an interconnect figure below it (A800, H800 SXM5, H800 PCIe); all are restricted today.

Plate II. One mark per tracked accelerator, dense FP16/BF16 compute (log) against memory bandwidth (log); ink encodes China export status, dashed strokes are estimated specifications, and concentric marks share identical published specs — 19 of 36 tracked parts are restricted for China. Arrows run from a part to the compliance variant cut from it; each mark links to its row in the register below, and pointing at a rule on the date rail rings the parts it newly restricted. The reference line is the 6,500 GB/s DRAM-bandwidth threshold, quoted as the controlling figure in the classification of B100, B200, MI350X. 7 of 36 tracked parts publish memory bandwidth but no dense FP16/BF16 figure and sit in the hatched left rail at the bandwidth they do publish; 6 of those publish an FP8 figure instead. 2 publish compute but no bandwidth and sit in the hatched band below the axis (H800 SXM5, H20E (HBM3E refresh)). 4 appear in neither. B30A, R100 (Rubin), Huawei Ascend 910D publish no figure on either axis, which is also why B30A carries no drawable connector to the part it was cut from. The Cerebras WSE-3 record marks its own memory-bandwidth figure as on-wafer SRAM fabric bandwidth rather than off-die memory bandwidth, which is not the quantity this axis measures, and its compute figure as a per-wafer aggregate rather than a per-die one; plotting it here would assert the comparison the record refuses.

The classification rules are written in two measures — how much dense arithmetic a part does, and how fast it can move weights through memory — so those are the axes. 8 tracked parts publish a memory bandwidth at or above the 6,500 GB/s DRAM threshold the classification prose cites, and 7 of those are restricted. 4 parts sit under case-by-case review with conditions attached. The highest-compute Chinese domestic part on record here publishes 900 TFLOPS dense, against 2,516.6 for the highest-compute part the field holds.

6 of the 36 tracked parts are compliance variants: an existing die cut down to clear a threshold. A800 on A100 SXM and H800 PCIe on H100 PCIe land exactly on top of the parts they were cut from, because what was reduced was interconnect bandwidth — which this field does not plot, and which the October 2023 rule superseded with a combined metric anyway. The variant whose position moved furthest, H20 SXM, publishes 148 TFLOPS dense against the H100 SXM5’s 989.5, while its memory bandwidth went the other way — 3,350 to 4,000 GB/s.

Plate data

Chip	Vendor	China status	FP16 dense	Mem BW
Cerebras WSE-3	Cerebras	Restricted	125,000	21,000,000
AMD Instinct MI355X	AMD	Restricted	2,516.6	8,000
MI350X	AMD	Restricted	2,309.6	8,000
B200	NVIDIA	Restricted	2,250	8,000
Gaudi 3	Intel	Restricted	1,835	3,700
B100	NVIDIA	Restricted	1,750	8,000
MI300X	AMD	Restricted	1,307.4	5,300
MI325X	AMD	Case-by-Case Review	1,307.4	6,000
H100 SXM5	NVIDIA	Restricted	989.5	3,350
H800 SXM5 ~	NVIDIA	Restricted	989.5	—
H200 SXM	NVIDIA	Case-by-Case Review	989.5	4,800
Google TPU v6e (Trillium)	Google	Not Export-Controlled	918	1,638
Huawei Ascend 920 ~	Huawei	Domestic (China)	900	4,000
H100 NVL	NVIDIA	Restricted	835.5	3,938
Huawei Ascend 910C ~	Huawei	Domestic (China)	780	3,200
H100 PCIe	NVIDIA	Restricted	756	2,000
H800 PCIe	NVIDIA	Restricted	756	2,000
Google TPU v5p	Google	Not Export-Controlled	459	2,575
Ascend 910B ~	Huawei	Domestic (China)	375	1,600
A100 SXM	NVIDIA	Restricted	312	2,039
A800	NVIDIA	Restricted	312	2,039
Google TPU v4	Google	Not Export-Controlled	275	1,200
TPU v5e	Google	Not Export-Controlled	197	819
H20 SXM ~	NVIDIA	Case-by-Case Review	148	4,000
H20E (HBM3E refresh) ~	NVIDIA	Case-by-Case Review	148	—
Tenstorrent Wormhole n300	Tenstorrent	Not Export-Controlled	131	576
AMD Instinct MI400 ~	AMD	Restricted	—	19,600
AWS Trainium3 ~	Amazon	Not Export-Controlled	—	4,900
B30A ~	NVIDIA	Designed Compliant	—	—
Gaudi 2 ~	Intel	Restricted	—	2,450
Google TPU v7 (Ironwood)	Google	Not Export-Controlled	—	7,370
Huawei Ascend 910D ~	Huawei	Domestic (China)	—	—
NVIDIA B300	NVIDIA	Restricted	—	8,000
NVIDIA R200 (Rubin) ~	NVIDIA	Restricted	—	22,000
R100 (Rubin) ~	NVIDIA	Restricted	—	—
Tenstorrent Blackhole p150	Tenstorrent	Not Export-Controlled	—	512

ReadingDense FP16/BF16 TFLOPS and memory bandwidth in GB/s, ordered as the field is, with unpublished figures left empty. 23 of these rows carry both measures and are drawn as marks; the rest sit in the rails or, for the 4 with nothing comparable to place, in this table alone.

The classification register

36 accelerators · 13 carry estimated specifications

Loading the register…

Family genealogy

NVIDIA Ampere NVIDIA

A100 SXM312 TFLOPS dense · Restricted · newly restricted 2022
NVLink 600→400 GB/s
A800312 TFLOPS dense · Restricted · newly restricted 2023

NVIDIA Hopper NVIDIA

H100 SXM5989.5 TFLOPS dense · Restricted · newly restricted 2022
Mem BW 3,350→2,000 GB/s; HBM3→HBM2e; FP16 989.5→756
H100 PCIe756 TFLOPS dense · Restricted
Mem BW 2,000→3,938 GB/s; Mem 80→94 GB; HBM2e→HBM3; FP16 756→835.5
H100 NVL835.5 TFLOPS dense · Restricted
NVLink 600→400 GB/s; Mem 94→80 GB; FP16 835.5→989.5; specs unverified
H800 SXM5989.5 TFLOPS dense · Restricted · newly restricted 2023
HBM3→HBM2e; FP16 989.5→756
H800 PCIe756 TFLOPS dense · Restricted · newly restricted 2023
NVLink 400→900 GB/s; Mem BW 2,000→4,800 GB/s; Mem 80→141 GB; HBM2e→HBM3E; FP16 756→989.5; Restricted → Case-by-Case Review
H200 SXM989.5 TFLOPS dense · Case-by-Case Review
Mem BW 4,800→4,000 GB/s; Mem 141→96 GB; HBM3E→HBM3; FP16 989.5→148; specs unverified
H20 SXM148 TFLOPS dense · Case-by-Case Review · newly restricted 2025
Mem 96→144 GB; HBM3→HBM3E
H20E (HBM3E refresh)148 TFLOPS dense · Case-by-Case Review · newly restricted 2025

NVIDIA Blackwell NVIDIA

B1001,750 TFLOPS dense · Restricted
FP16 1750→2250
B2002,250 TFLOPS dense · Restricted
Mem 192→288 GB; HBM3E→HBM3e
NVIDIA B300no dense FP16/BF16 figure published · Restricted
Mem 288→144 GB; HBM3e→HBM3E; specs unverified; Restricted → Designed Compliant
B30Ano dense FP16/BF16 figure published · Designed Compliant

NVIDIA Rubin NVIDIA

R100 (Rubin)no dense FP16/BF16 figure published · Restricted
same compute, different policy
NVIDIA R200 (Rubin)no dense FP16/BF16 figure published · Restricted

AMD Instinct AMD

MI300X1,307.4 TFLOPS dense · Restricted
Mem BW 5,300→6,000 GB/s; Mem 192→256 GB; HBM3→HBM3E; Restricted → Case-by-Case Review
MI325X1,307.4 TFLOPS dense · Case-by-Case Review
Mem BW 6,000→8,000 GB/s; Mem 256→288 GB; FP16 1307.4→2309.6; Case-by-Case Review → Restricted
MI350X2,309.6 TFLOPS dense · Restricted
FP16 2309.6→2516.6
AMD Instinct MI355X2,516.6 TFLOPS dense · Restricted
Mem BW 8,000→19,600 GB/s; Mem 288→432 GB; HBM3E→HBM4; specs unverified
AMD Instinct MI400no dense FP16/BF16 figure published · Restricted

Huawei Ascend Huawei

Ascend 910B375 TFLOPS dense · Domestic (China)
Mem BW 1,600→3,200 GB/s; Mem 64→128 GB; HBM2e→HBM
Huawei Ascend 910C780 TFLOPS dense · Domestic (China)
same compute, different policy
Huawei Ascend 910Dno dense FP16/BF16 figure published · Domestic (China)
same compute, different policy
Huawei Ascend 920900 TFLOPS dense · Domestic (China)

Intel Gaudi Intel

Gaudi 2no dense FP16/BF16 figure published · Restricted
Mem BW 2,450→3,700 GB/s; Mem 96→128 GB
Gaudi 31,835 TFLOPS dense · Restricted

Google TPU Google

Google TPU v4275 TFLOPS dense · Not Export-Controlled
Mem BW 1,200→819 GB/s; Mem 32→16 GB; HBM2→HBM2e
TPU v5e197 TFLOPS dense · Not Export-Controlled
Mem BW 819→2,575 GB/s; Mem 16→95 GB
Google TPU v5p459 TFLOPS dense · Not Export-Controlled
NVLink 1200→800 GB/s; Mem BW 2,575→1,638 GB/s; Mem 95→32 GB; HBM2e→HBM
Google TPU v6e (Trillium)918 TFLOPS dense · Not Export-Controlled
Mem BW 1,638→7,370 GB/s; Mem 32→192 GB; HBM→HBM3e
Google TPU v7 (Ironwood)no dense FP16/BF16 figure published · Not Export-Controlled

AWS Trainium Amazon

AWS Trainium3no dense FP16/BF16 figure published · Not Export-Controlled

Cerebras Wafer-Scale Engine Cerebras

Cerebras WSE-3125,000 TFLOPS dense · Restricted

Tenstorrent Tenstorrent

Tenstorrent Wormhole n300131 TFLOPS dense · Not Export-Controlled
Mem BW 576→512 GB/s; Mem 24→32 GB
Tenstorrent Blackhole p150no dense FP16/BF16 figure published · Not Export-Controlled

Plate III. One lane per family, generations left to right in catalog order (the substrate records no per-part release date, so position is ordinal, not time). Node ink is China export status on the same encoding as Plate II; a year stamped beneath a node is a rule naming that part as newly restricted; an arc joins a compliance variant to the part it was cut from where the two are more than one generation apart. Gap text is the first recorded change between consecutive generations, clipped to the gap — the full delta reads on hover, and in the stacked form this figure takes on narrow screens.

The threshold rules

2022-10-13October 2022 Advanced Computing Rule87 FR 62186
Compute performance (TFLOPS) and interconnect bandwidth
ECCN 3A090: chips with peak performance ≥300 TFLOPS (aggregate bidirectional transfer rate ≥600 GB/s) or ≥600 TOPS (certain configurations). Caught A100 and H100; A800 designed to comply via reduced interconnect.
Oct 2022 interconnect threshold (600 GB/s) — 600 GB/s
Newly restricted: A100 SXM, H100 SXM5.
2023-10-25October 2023 Advanced Computing Update88 FR 73458
Total Processing Performance (TPP): 2 × MacTOPS × bit-length, summed across processing units
Introduced TPP metric combining compute and bandwidth. Closed the A800/H800 interconnect-reduction loophole. Also broadened end-use controls.
Newly restricted: A800, H800 SXM5, H800 PCIe.
2024-12-02December 2024 Expansion89 FR 96790
Extended to HBM bandwidth thresholds; added 140+ Chinese entities
Added HBM bandwidth as a classification criterion. HBM2E and above restricted. Expanded entity list significantly.
No tracked part was newly restricted by this action.
2025-04-15April 2025 H20 License Requirementno Federal Register citation on record
No new threshold metric. License-required determination on the previously-compliant-by-design H20.
BIS imposed a license requirement (presumption of denial) on H20 exports to China. Triggered by evidence that H20's retained 900 GB/s NVLink allowed multi-GPU aggregation approaching banned-chip throughput — the loophole the Oct 2023 TPP rule had not closed. NVIDIA took a $5.5B inventory write-down. AMD's comparable MI308 was also covered.
Newly restricted: H20 SXM, H20E (HBM3E refresh).
2025-07-15July 2025 H20 Re-License Frameworkno Federal Register citation on record
Conditional license approval with a 15% US-revenue-share condition. No technical metric change.
Trump administration approved H20 and AMD MI308 licenses to China conditional on NVIDIA and AMD remitting 15% of China-derived chip revenue to the US Treasury. H20 returned to case-by-case licensed-export status under this framework.
No tracked part was newly restricted by this action.
2026-01-15January 2026 License Review Policy Revision91 FR 1684
No new threshold. Changed review standard for H200-class chips.
Shifted H200 and MI325X exports to China from presumption of denial to case-by-case review. Conditions: ≤50% China volume, compliance certification, third-party testing. Explicitly NAMES only H200 and MI325X — H20 is NOT covered by this revision and remains under the July 2025 licensed-export regime.
No tracked part was newly restricted by this action.

How each family moved

NVIDIA Ampere NVIDIA: A100 restricted (Oct 2022) → A800 compliance variant (interconnect reduction) → A800 restricted (Oct 2023 TPP metric)
NVIDIA Hopper NVIDIA: H100 SXM5/PCIe/NVL all restricted (Oct 2022) → H800 SXM5 + PCIe compliance variants (NVLink + HBM BW reduction) → H800 family restricted (Oct 2023) → H20 designed-compliant post-Oct-2023 TPP rule (148 BF16 dense / 96 GB HBM3 / NVLink full 900 GB/s — the loophole) → H20 license-required Apr 2025 → H20 re-licensed Jul 2025 under 15% revenue-share framework → H20E HBM3E refresh (144 GB) → H200 case-by-case (Jan 2026, H200+MI325X only — H20 not covered). H800 + H20 both sold via Chinese OEM channel only — no public NVIDIA datasheets exist.
NVIDIA Blackwell NVIDIA: B100 (700W, 1,750 dense BF16 TFLOPS, drop-in HGX H100 compatible) → B200 (1000W, 2,250 dense BF16; exceeds TPP 21,000 + DRAM BW 6,500 GB/s) → B300 Blackwell Ultra (same die, more memory, 288GB HBM3e) → B30A compliance variant (single-die, ~50% perf, specs unverified).
NVIDIA Rubin NVIDIA: R100 announced GTC 2025 → R200 announced GTC 2026 (50 PFLOPS FP4, TSMC 3nm, 288GB HBM4, 22 TB/s). Mass production Q3-Q4 2026. VR200 NVL72 = ~1 exaFLOP FP8 per rack. Rubin Ultra planned H2 2027.
AMD Instinct AMD: MI300X restricted (CDNA 3, 1.3 PFLOPS FP8) → MI325X case-by-case (Jan 2026, CDNA 3, 256GB HBM3E) → MI350X restricted (CDNA 4 air-cooled, 9.2 PFLOPS FP8 dense, 1000W) → MI355X CDNA 4 liquid-cooled (10.1 PFLOPS FP8 dense, 20.1 PFLOPS FP4, 1400W) → MI400 CDNA 5 (20 PFLOPS FP8, 40 PFLOPS FP4, 432GB HBM4, 2026 target).
Huawei Ascend Huawei: 910B (~256 FP16 TFLOPS, SMIC 7nm) → 910C (780 BF16, ~60% H100 inference per DeepSeek, CloudMatrix 384) → 910D (5nm, 4-die, competing with Blackwell, mass production Q2-Q3 2026) → 920 (900 BF16, SMIC 6nm-class, H2 2025, H20 replacement). All constrained by HBM supply and no domestic EUV.
Intel Gaudi Intel: Gaudi 2 uses TSMC 7nm; Gaudi 3 uses TSMC 5nm with Intel EMIB packaging. Ethernet-based interconnect (not NVLink). Deployed by Meta, available on AWS. Both restricted to China.
Google TPU Google: v4 (275 BF16 TFLOPS, 32 GiB HBM2, 170 W, 7nm, 2021) → v5e (197 BF16, 16 GB HBM2e — efficiency-oriented) → v5p (459 BF16, 95 GiB HBM2e, ICI 1.2 TB/s — training-oriented, 2023) → v6e Trillium (918 BF16, 32 GB HBM, ICI 800 GB/s, 2024) → v7 Ironwood (4,614 FP8, 192 GB HBM3e, 960 W, 2025). Internal chips, not sold. Cloud access controlled by service policies. Anthropic committed >1M Ironwood chips beginning 2026.
AWS Trainium Amazon: Trainium3 (2.52 PFLOPs FP8, 144GB HBM3e, TSMC N3). GA Dec 2025. EC2 Trn3 UltraServers up to 144 chips. Internal chip, not sold — cloud access only.
Cerebras Wafer-Scale Engine Cerebras: WSE-3 (wafer-scale: 46,225 mm², 4T transistors, 900K AI cores, 125 PFLOPS peak, TSMC 5nm). Released March 2024. Per-wafer aggregate; not directly per-die-equivalent to NVIDIA/AMD GPUs. CS-3 supercomputer named TIME "best inventions of 2024".
Tenstorrent Tenstorrent: Wormhole n300 (2024: 131 FP16 / 262 BLOCKFP8 TFLOPS, 24 GB GDDR6, 300 W, GlobalFoundries 12 nm) → Blackhole p150 (2025: 664 BLOCKFP8 TFLOPS, 32 GB GDDR6, 300 W, GlobalFoundries 6 nm, 4× QSFP-DD 800G Ethernet scale-out). Ethernet-based scale-out (not NVLink); RISC-V control cores; open-source ML stack (tt-metal / tt-NN).

How a chip is classified

Export control status follows from the specifications against the BIS threshold metrics (ECCN 3A090 and the Total Processing Performance measure). Specifications come from primary vendor datasheets where one exists; where none does, the figures are industry estimates and the record says so — 13 of 36 parts carry the estimated flag, drawn with a dashed stroke and prefixed with a tilde in the register. Huawei publishes no Ascend datasheet, and the NVIDIA parts sold only through the Chinese OEM channel have none either.

Status is stated as of the most recent BIS action on record here, the January 2026 policy revision. Domestic Chinese parts fall outside US export controls directly, but their fabricators inherit equipment restrictions that constrain them indirectly — which is why the domestic rows are drawn as open marks rather than left off the field.

Memory

Process

Tenstorrent Blackhole p150

Tenstorrent

—

512

32 GB GDDR6

—

Not Export-Controlled

AWS Trainium3

Amazon

—

4,900

144 GB HBM3e

TSMC N3

Not Export-Controlled

Google TPU v7 (Ironwood)

Google

—

7,370

192 GB HBM3e

—

Not Export-Controlled

Tenstorrent Wormhole n300

Tenstorrent

131

576

24 GB GDDR6

—

Not Export-Controlled

TPU v5e

Google

—

819

16 GB HBM2e

—

Not Export-Controlled

Google TPU v4

Google

—

1,200

32 GB HBM2

7nm

Not Export-Controlled

Google TPU v5p

Google

—

2,575

95 GB HBM2e

—

Not Export-Controlled

Google TPU v6e (Trillium)

Google

—

1,638

32 GB HBM

—

Not Export-Controlled

Huawei Ascend 910D

Huawei

—

5nm

Domestic (China)

Ascend 910B

Huawei

375

1,600

64 GB HBM2e

SMIC N+2 (~7nm class, 2nd-gen)

Domestic (China)

Huawei Ascend 910C

Huawei

—

3,200

128 GB HBM

SMIC N+2 (~7nm class, 2nd-gen)

Domestic (China)

Huawei Ascend 920

Huawei

—

4,000

—

SMIC N+3 (6nm-class)

Domestic (China)

B30A variant

NVIDIA

—

144 GB HBM3E

TSMC (node unconfirmed)

Designed Compliant

H20E (HBM3E refresh) variant

NVIDIA

148

—

144 GB HBM3E

TSMC 4N

Case-by-Case Review

H20 SXM variant

NVIDIA

148

4,000

96 GB HBM3

TSMC 4N

Case-by-Case Review

H200 SXM

NVIDIA

989.5

4,800

141 GB HBM3E

TSMC 4N

Case-by-Case Review

FP16 dense989.5 TFLOPS

FP16 sparse1,979 TFLOPS

BF16 dense989.5 TFLOPS

TF32 dense494.7 TFLOPS

TF32 sparse989.5 TFLOPS

FP8 dense1,979 TFLOPS

FP8 sparse3,958 TFLOPS

FP4 dense—

FP4 sparse—

INT81,979 TOPS

Memory141 GB HBM3E

Memory bandwidth4,800 GB/s

Interconnect bandwidth900 GB/s

Thermal design power700 W

Process nodeTSMC 4N

ArchitectureHopper

Compliance variant of—

Regulatory basis

Jan 15, 2026 BIS policy revision

Conditions

Conditions: (1) China volumes ≤50% of US domestic sales; (2) purchaser compliance certification; (3) third-party performance/security testing in US

Source

Primary source NVIDIA H200 datasheet; BIS Jan 2026 press release — open

Notes

Same compute die as H100 (FP16 dense 989.5 TFLOPS). 141 GB HBM3E at 4,800 GB/s. Jan 2026 policy shifted from presumption of denial to case-by-case review with material conditions.

MI325X

AMD

1,307.4

6,000

256 GB HBM3E

TSMC 5nm/6nm

Case-by-Case Review

AMD Instinct MI400

AMD

—

19,600

432 GB HBM4

—

Restricted

NVIDIA R200 (Rubin)

NVIDIA

—

22,000

288 GB HBM4

TSMC N3

Restricted

NVIDIA B300

NVIDIA

—

8,000

288 GB HBM3e

TSMC N4

Restricted

Gaudi 2

Intel

—

2,450

96 GB HBM2e

TSMC 7nm

Restricted

R100 (Rubin)

NVIDIA

—

TSMC 3nm

Restricted

A800 variant

NVIDIA

312

2,039

80 GB HBM2e

TSMC 7nm

Restricted

A100 SXM

NVIDIA

312

2,039

80 GB HBM2e

TSMC 7nm

Restricted

H800 PCIe variant

NVIDIA

756

2,000

80 GB HBM2e

TSMC 4N

Restricted

H100 PCIe

NVIDIA

756

2,000

80 GB HBM2e

TSMC 4N

Restricted

H100 NVL

NVIDIA

835.5

3,938

94 GB HBM3

TSMC 4N

Restricted

H800 SXM5 variant

NVIDIA

989.5

—

80 GB HBM3

TSMC 4N

Restricted

H100 SXM5

NVIDIA

989.5

3,350

80 GB HBM3

TSMC 4N

Restricted

MI300X

AMD

1,307.4

5,300

192 GB HBM3

TSMC 5nm/6nm

Restricted

B100

NVIDIA

1,750

8,000

192 GB HBM3E

TSMC 4NP

Restricted

Gaudi 3

Intel

—

3,700

128 GB HBM2e

TSMC 5nm

Restricted

B200

NVIDIA

2,250

8,000

192 GB HBM3E

TSMC 4NP

Restricted

MI350X

AMD

2,309.6

8,000

288 GB HBM3E

TSMC N3P + N6

Restricted

AMD Instinct MI355X

AMD

2,516.6

8,000

288 GB HBM3E

TSMC N3P + N6

Restricted

Cerebras WSE-3

Cerebras

125,000

21,000,000

44 GB On-chip SRAM

TSMC 5nm

Restricted

NVIDIA Spec Sheets	T1 · primary	16 records
AMD Spec Sheets	T1 · primary	5 records
CSET Georgetown (Ascend specifications)	T2 · research	4 records
TrendForce industry estimates	T3 · analyst
Federal Register (control thresholds)	T1 · primary

NVIDIA Spec Sheets	T1 · primary	16 records
AMD Spec Sheets	T1 · primary	5 records
CSET Georgetown (Ascend specifications)	T2 · research	4 records
TrendForce industry estimates	T3 · analyst
Federal Register (control thresholds)	T1 · primary