Tracked accelerators on the two measures the export rules are written in, dense FP16/BF16 throughput and memory bandwidth, with the control thresholds drawn and each chip’s recorded China export status.
Control actions in this dataset, 2022–2026.
20 of 23 plotted chips meet the 4,800 TPP threshold at 16 bits.
3 chips report interconnect bandwidth below the October 2022 criterion of 600 GB/s (A800, H800 SXM5, H800 PCIe). Interconnect is a separate measure from the memory bandwidth on the vertical axis; the October 2023 update dropped the criterion.
Dense FP16/BF16 compute and memory bandwidth, on logarithmic axes. Concentric circles share the same values on both axes; arrows run from a parent chip to its compliance variant.
The horizontal line marks 6,500 GB/s memory bandwidth, cited in the classification entries for B100, B200, MI350X. The vertical line translates ECCN 3A090.a.1’s 4,800 TPP threshold into dense 16-bit throughput (300 TFLOPS, 88 FR 73458).
The left margin holds 6 chips with memory bandwidth but no dense FP16/BF16 specification; 5 have FP8 specifications. The bottom margin holds 2 with compute but no memory bandwidth (H800 SXM5, H20E (HBM3E refresh)). 4 chips cannot be plotted. B30A, Huawei Ascend 910D have neither specification. Cerebras WSE-3 reports wafer-scale compute and on-wafer SRAM bandwidth; Tenstorrent Wormhole n300 reports two-chip board totals. Those figures are excluded from the per-die comparison plotted here.
7 of the 8 tracked accelerators at or above 6,500 GB/s memory bandwidth are recorded as restricted for China. Among the chips plotted here, the highest published dense FP16/BF16 throughput for a Chinese domestic accelerator is 900 TFLOPS, compared with 4,000 TFLOPS across all vendors.
6 of the 35 tracked accelerators were designed as compliance variants of existing chips. A800 / A100 SXM and H800 PCIe / H100 PCIe overlap because each pair publishes the same compute and memory bandwidth. H20 SXM shows the largest shift from its parent on these logarithmic axes: 148 dense TFLOPS compared with 989.5 for H100 SXM5. Its memory bandwidth rose from 3,350 to 4,000 GB/s.
| Chip | Vendor | China status | Dense FP16/BF16 | Mem BW |
|---|---|---|---|---|
| NVIDIA Rubin GPU ~ | NVIDIA | Restricted | 4,000 | 22,000 |
| AMD Instinct MI355X | AMD | Restricted | 2,516.6 | 8,000 |
| MI350X | AMD | Restricted | 2,309.6 | 8,000 |
| B200 | NVIDIA | Restricted | 2,250 | 8,000 |
| Gaudi 3 | Intel | Restricted | 1,835 | 3,700 |
| B100 | NVIDIA | Restricted | 1,750 | 8,000 |
| MI300X | AMD | Restricted | 1,307.4 | 5,300 |
| MI325X | AMD | Case-by-Case Review | 1,307.4 | 6,000 |
| H100 SXM5 | NVIDIA | Restricted | 989.5 | 3,350 |
| H800 SXM5 ~ | NVIDIA | Restricted | 989.5 | — |
| H200 SXM | NVIDIA | Case-by-Case Review | 989.5 | 4,800 |
| Google TPU v6e (Trillium) | Unassessed | 918 | 1,638 | |
| Huawei Ascend 920 ~ | Huawei | Domestic (China) | 900 | 4,000 |
| H100 NVL | NVIDIA | Restricted | 835.5 | 3,938 |
| Huawei Ascend 910C ~ | Huawei | Domestic (China) | 780 | 3,200 |
| H100 PCIe | NVIDIA | Restricted | 756 | 2,000 |
| H800 PCIe | NVIDIA | Restricted | 756 | 2,000 |
| Google TPU v5p | Unassessed | 459 | 2,575 | |
| Ascend 910B ~ | Huawei | Domestic (China) | 375 | 1,600 |
| A100 SXM | NVIDIA | Restricted | 312 | 2,039 |
| A800 | NVIDIA | Restricted | 312 | 2,039 |
| Google TPU v4 | Unassessed | 275 | 1,200 | |
| TPU v5e | Unassessed | 197 | 819 | |
| H20 SXM ~ | NVIDIA | Case-by-Case Review | 148 | 4,000 |
| H20E (HBM3E refresh) ~ | NVIDIA | Unassessed | 148 | — |
| AMD Instinct MI400 ~ | AMD | Restricted | — | 19,600 |
| AWS Trainium3 ~ | Amazon | Unassessed | — | 4,900 |
| B30A ~ | NVIDIA | Designed Compliant | — | — |
| Gaudi 2 ~ | Intel | Restricted | — | 2,450 |
| Google TPU v7 (Ironwood) | Unassessed | — | 7,370 | |
| Huawei Ascend 910D ~ | Huawei | Domestic (China) | — | — |
| NVIDIA B300 | NVIDIA | Restricted | — | 8,000 |
| Tenstorrent Blackhole p150 | Tenstorrent | Unassessed | — | 512 |
| Cerebras WSE-3 · Wafer-scale system; not plotted | Cerebras | Unassessed | — | 21,000,000 |
| Tenstorrent Wormhole n300 · Two-chip board totals; not plotted | Tenstorrent | Unassessed | 131 | 576 |
ReadingDense FP16/BF16 compute is in TFLOPS; memory bandwidth is in GB/s. Board and wafer-scale totals appear last, outside the per-chip throughput ordering.
Accelerators with a calculable TPP meet or exceed this threshold.
Accelerators above the threshold with a recorded China status other than “Restricted” (ringed) — Blackhole p150 (unassessed), Ascend 910B (domestic (china)), TPU v5p (unassessed), Ascend 910C (domestic (china)), B30A (designed compliant), Ascend 920 (domestic (china)) and 5 more.
Nearest below the line: TPU v4 at TPP 4,400 (8.3% below the parameter). Nearest above: A100 SXM at TPP 4,992 (4% above the parameter).
TPP uses dense throughput at each chip’s highest published basis under ECCN 3A090 (88 FR 73458); the default threshold is 4,800. Board totals and peaks without a verified dense basis are excluded.
TPP could not be calculated for Gaudi 2, Cerebras WSE-3, Tenstorrent Wormhole n300, Huawei Ascend 910D from the available specifications. ECCN 3A090.a.2 also covers TPP ≥ 1,600 with performance density ≥ 5.92. This calculation requires applicable die area, which is unavailable in this dataset. Chips below 4,800 TPP may therefore still meet that criterion.
Loading accelerators…
Comparison 1 · NVIDIA Ampere
| Measure | From | To | Unit |
|---|---|---|---|
| Interconnect | 600 | 400 | GB/s |
The later model is recorded as a compliance variant of the earlier model.
Families tracked, 35 parts in all; the longest lane is NVIDIA Hopper with 8 models.
Compliance variants designed to meet export-control thresholds. Arcs connect variants to their parent chips across intervening models.
Adjacent model pairs with different recorded China export statuses.
Chips newly restricted by one of the listed actions; the year appears below each chip.
2022-10-21October 2022 Advanced Computing Rule87 FR 62186
Compute performance (TFLOPS) and interconnect bandwidth
ECCN 3A090 combined an aggregate bidirectional transfer rate of at least 600 GB/s to or from other ICs, excluding volatile memories, with compute criteria equivalent to at least 4,800 bits × TOPS. Both bandwidth and compute conditions had to be met.
Oct 2022 interconnect threshold (600 GB/s) — 600 GB/s
Newly restricted: A100 SXM, H100 SXM5.
2023-11-17October 2023 Advanced Computing Update88 FR 73458
Total Processing Performance (TPP): 2 × MacTOPS × bit-length, summed across processing units
Introduced the TPP metric — dense throughput × bit-length of the operation, evaluated at the highest value across supported bit-lengths, dense matrices only. Closed the A800/H800 interconnect-reduction loophole. Also broadened end-use controls. 3A090.a also has a second leg (TPP ≥ 1,600 with performance density ≥ 5.92) that requires applicable die area, which no record here publishes.
ECCN 3A090.a — 4,800 TPP (2 × MacTOPS × bit-length; verified against 88 FR 73458 and the current CCL)
Newly restricted: A800, H800 SXM5, H800 PCIe.
2024-12-02December 2024 Expansion89 FR 96790
HBM memory bandwidth density
Added ECCN 3A090.c for HBM above 2 GB/s/mm² of memory bandwidth density, calculated from package or stack bandwidth and area. Certain co-packaged HBM-and-logic ICs whose dominant function is processing are excluded. The rule took effect December 2; compliance with the HBM provisions began December 31, 2024.
No newly restricted chips are recorded here for this action.
2025-04-09April 2025 H20 License RequirementNVIDIA Form 8-K
No new threshold metric. License-required determination on the previously-compliant-by-design H20.
NVIDIA reported an April 9 government notice requiring licenses for H20 and other ICs meeting specified H20 bandwidth characteristics. It covered exports to China, including Hong Kong and Macau, D:5 countries, and companies headquartered or with an ultimate parent there. NVIDIA disclosed the notice on April 15.
Newly restricted: H20 SXM.
2025-07-14July 2025 H20 Licensing AnnouncementNVIDIA announcementNVIDIA August 2025 filing
Announcement of expected licensing; no technical threshold change.
NVIDIA announced assurances that licenses would be granted. Its August 2025 filing later confirmed licenses for selected H20 customers, and described a 15% revenue-share expectation from U.S. officials with no codifying regulation at that time.
No newly restricted chips are recorded here for this action.
2026-01-15January 2026 License Review Policy Revision91 FR 1684
Conditional case-by-case licensing pathway for H200-class chips.
Provides case-by-case review for qualifying US exports to China or Macau below 21,000 TPP and 6,500 GB/s total DRAM bandwidth. H200 and MI325X are examples. Approval depends on the rule’s supply, aggregate-TPP, end-use, security and testing conditions.
No newly restricted chips are recorded here for this action.
Under the October 2023 Advanced Computing Update, TPP is 2 × MacTOPS × bit-length, summed across processing units (88 FR 73458). For dense FP16, this is 16 times the published TFLOPS. The calculation uses the highest TPP available across each chip’s published bit-lengths, and each result is compared with the ECCN 3A090.a threshold of 4,800. Licensing also depends on the transaction and the other applicable controls.
9 of the 35 accelerators have no dense FP16/BF16 specification in this dataset; other published precisions can still support a TPP calculation. TPP cannot be evaluated for 4 chips, which publish no dense per-IC figure.
6 accelerators are offered through Google Cloud or AWS, and the cited product documentation classifies none of them for China export. 4 have a dense-FP16/BF16-based TPP above the H20 SXM’s 2,368, the lowest such reading among chips newly restricted by the actions listed here.
For restrictions on semiconductor manufacturing equipment, see supply-chain chokepoints.
| Memory | Process | |||||
|---|---|---|---|---|---|---|
| NVIDIA Rubin GPU | NVIDIA | 4,000 | 22,000 | 288 GB HBM4 | — | Restricted |
| AMD Instinct MI355X | AMD | 2,516.6 | 8,000 | 288 GB HBM3E | TSMC N3P + N6 | Restricted |
| MI350X | AMD | 2,309.6 | 8,000 | 288 GB HBM3E | TSMC N3P + N6 | Restricted |
| B200 | NVIDIA | 2,250 | 8,000 | 192 GB HBM3E | TSMC 4NP | Restricted |
| Gaudi 3 | Intel | 1,835 | 3,700 | 128 GB HBM2e | TSMC 5nm | Restricted |
| B100 | NVIDIA | 1,750 | 8,000 | 192 GB HBM3E | TSMC 4NP | Restricted |
| MI300X | AMD | 1,307.4 | 5,300 | 192 GB HBM3 | TSMC 5nm/6nm | Restricted |
| H100 SXM5 | NVIDIA | 989.5 | 3,350 | 80 GB HBM3 | TSMC 4N | Restricted |
| H800 SXM5 variant | NVIDIA | 989.5 | — | 80 GB HBM3 | TSMC 4N | Restricted |
| H100 NVL | NVIDIA | 835.5 | 3,938 | 94 GB HBM3 | TSMC 4N | Restricted |
| H100 PCIe | NVIDIA | 756 | 2,000 | 80 GB HBM2e | TSMC 4N | Restricted |
| H800 PCIe variant | NVIDIA | 756 | 2,000 | 80 GB HBM2e | TSMC 4N | Restricted |
| A100 SXM | NVIDIA | 312 | 2,039 | 80 GB HBM2e | TSMC 7nm | Restricted |
| A800 variant | NVIDIA | 312 | 2,039 | 80 GB HBM2e | TSMC 7nm | Restricted |
| AMD Instinct MI400 | AMD | — | 19,600 | 432 GB HBM4 | — | Restricted |
| Gaudi 2 | Intel | — | 2,450 | 96 GB HBM2e | TSMC 7nm | Restricted |
| NVIDIA B300 | NVIDIA | — | 8,000 | 288 GB HBM3E | TSMC N4 | Restricted |
| MI325X | AMD | 1,307.4 | 6,000 | 256 GB HBM3E | TSMC 5nm/6nm | Case-by-Case Review |
| H200 SXM | NVIDIA | 989.5 | 4,800 | 141 GB HBM3E | TSMC 4N | Case-by-Case Review |
| H20 SXM variant | NVIDIA | 148 | 4,000 | 96 GB HBM3 | TSMC 4N | Case-by-Case Review |
| B30A variant | NVIDIA | — | — | 144 GB HBM3E | TSMC (node unconfirmed) | Designed Compliant |
| Huawei Ascend 920 | Huawei | 900 | 4,000 | — | SMIC N+3 (6nm-class) | Domestic (China) |
| Huawei Ascend 910C | Huawei | 780 | 3,200 | 128 GB HBM | SMIC N+2 (~7nm class, 2nd-gen) | Domestic (China) |
FP16 dense— FP16 sparse— BF16 dense780 TFLOPS TF32 dense— TF32 sparse— FP8 dense— FP8 sparse— FP4 dense— FP4 sparse— INT8— Memory128 GB HBM Memory bandwidth3,200 GB/s Interconnect bandwidth— Thermal design power700 W Process nodeSMIC N+2 (~7nm class, 2nd-gen) ArchitectureDa Vinci Compliance variant of— Total Processing Performance12,480 (BF16 × bit-length; ≈2.6× the 3A090.a parameter) Regulatory basis Named in BIS’s May 2025 guidance on chips presumptively subject to General Prohibition 10. Chinese design does not establish an exemption from the EAR. Status sourceConditions None recorded. Source Research database DeepSeek research / Tom's Hardware — open Notes The cited reporting attributes the compute chiplet to SMIC N+2. Reported BF16 throughput differs: this dataset holds 780 TFLOPS, while Epoch AI lists 800. CloudMatrix 384 is reported at 300 BF16 PFLOPS across 384 chips. Specifications remain estimates; the source of the per-chip discrepancy is not established here. Recorded deployments This accelerator is not named in the GPU inventories held for 9 facilities. Country access Not covered in the 26 country access profiles. Browse country coverage. | ||||||
| Ascend 910B | Huawei | 375 | 1,600 | 64 GB HBM2e | SMIC N+2 (~7nm class, 2nd-gen) | Domestic (China) |
| Huawei Ascend 910D | Huawei | — | — | — | 5nm | Domestic (China) |
| Google TPU v6e (Trillium) | 918 | 1,638 | 32 GB HBM | — | Unassessed | |
| Google TPU v5p | 459 | 2,575 | 95 GB HBM2e | — | Unassessed | |
| Google TPU v4 | 275 | 1,200 | 32 GB HBM2 | 7nm | Unassessed | |
| TPU v5e | 197 | 819 | 16 GB HBM2e | — | Unassessed | |
| H20E (HBM3E refresh) variant | NVIDIA | 148 | — | 144 GB HBM3E | TSMC 4N | Unassessed |
| AWS Trainium3 | Amazon | — | 4,900 | 144 GB HBM3E | TSMC N3 | Unassessed |
| Cerebras WSE-3 | Cerebras | — | 21,000,000 † | 44 GB On-chip SRAM | TSMC 5nm | Unassessed |
| Google TPU v7 (Ironwood) | — | 7,370 | 192 GB HBM3E | — | Unassessed | |
| Tenstorrent Blackhole p150 | Tenstorrent | — | 512 | 32 GB GDDR6 | — | Unassessed |
| Tenstorrent Wormhole n300 | Tenstorrent | 131 † | 576 † | 24 GB GDDR6 | — | Unassessed |
†Values marked † are excluded from the per-chip ranking.
