Checked 2026-09-09 · unchanged since 2026-08-21RSS

Export Controls

Export restrictions matched to the chips and facilities they reach, and to semiconductor trade before and after each action.

17 of 35 tracked accelerators are restricted for China

Tracked accelerators on the two measures the export rules are written in, dense FP16/BF16 throughput and memory bandwidth, with the control thresholds drawn and each chip’s recorded China export status.

Inspect a chip

Select a mark or choose a name to read its specifications and classification.

Restricted

Recorded as restricted for China under a cited control action.

Case-by-Case Review

Licence required, reviewed case by case, with conditions attached.

Designed Compliant

Designed to meet export-control thresholds.

Domestic (China)

Chinese-designed accelerators; US export controls can still apply.

Unassessed

No China export classification is recorded for these chips.

Estimated specifications

Dashed outlines in the charts and a tilde in the table mark estimated specifications.

Control actions in this dataset, 2022–2026.

20 of 23 plotted chips meet the 4,800 TPP threshold at 16 bits.

3 chips report interconnect bandwidth below the October 2022 criterion of 600 GB/s (A800, H800 SXM5, H800 PCIe). Interconnect is a separate measure from the memory bandwidth on the vertical axis; the October 2023 update dropped the criterion.

Dense FP16/BF16 compute and memory bandwidth, on logarithmic axes. Concentric circles share the same values on both axes; arrows run from a parent chip to its compliance variant.

The horizontal line marks 6,500 GB/s memory bandwidth, cited in the classification entries for B100, B200, MI350X. The vertical line translates ECCN 3A090.a.1’s 4,800 TPP threshold into dense 16-bit throughput (300 TFLOPS, 88 FR 73458).

The left margin holds 6 chips with memory bandwidth but no dense FP16/BF16 specification; 5 have FP8 specifications. The bottom margin holds 2 with compute but no memory bandwidth (H800 SXM5, H20E (HBM3E refresh)). 4 chips cannot be plotted. B30A, Huawei Ascend 910D have neither specification. Cerebras WSE-3 reports wafer-scale compute and on-wafer SRAM bandwidth; Tenstorrent Wormhole n300 reports two-chip board totals. Those figures are excluded from the per-die comparison plotted here.

7 of the 8 tracked accelerators at or above 6,500 GB/s memory bandwidth are recorded as restricted for China. Among the chips plotted here, the highest published dense FP16/BF16 throughput for a Chinese domestic accelerator is 900 TFLOPS, compared with 4,000 TFLOPS across all vendors.

6 of the 35 tracked accelerators were designed as compliance variants of existing chips. A800 / A100 SXM and H800 PCIe / H100 PCIe overlap because each pair publishes the same compute and memory bandwidth. H20 SXM shows the largest shift from its parent on these logarithmic axes: 148 dense TFLOPS compared with 989.5 for H100 SXM5. Its memory bandwidth rose from 3,350 to 4,000 GB/s.

Chart data

Chip	Vendor	China status	Dense FP16/BF16	Mem BW
NVIDIA Rubin GPU ~	NVIDIA	Restricted	4,000	22,000
AMD Instinct MI355X	AMD	Restricted	2,516.6	8,000
MI350X	AMD	Restricted	2,309.6	8,000
B200	NVIDIA	Restricted	2,250	8,000
Gaudi 3	Intel	Restricted	1,835	3,700
B100	NVIDIA	Restricted	1,750	8,000
MI300X	AMD	Restricted	1,307.4	5,300
MI325X	AMD	Case-by-Case Review	1,307.4	6,000
H100 SXM5	NVIDIA	Restricted	989.5	3,350
H800 SXM5 ~	NVIDIA	Restricted	989.5	—
H200 SXM	NVIDIA	Case-by-Case Review	989.5	4,800
Google TPU v6e (Trillium)	Google	Unassessed	918	1,638
Huawei Ascend 920 ~	Huawei	Domestic (China)	900	4,000
H100 NVL	NVIDIA	Restricted	835.5	3,938
Huawei Ascend 910C ~	Huawei	Domestic (China)	780	3,200
H100 PCIe	NVIDIA	Restricted	756	2,000
H800 PCIe	NVIDIA	Restricted	756	2,000
Google TPU v5p	Google	Unassessed	459	2,575
Ascend 910B ~	Huawei	Domestic (China)	375	1,600
A100 SXM	NVIDIA	Restricted	312	2,039
A800	NVIDIA	Restricted	312	2,039
Google TPU v4	Google	Unassessed	275	1,200
TPU v5e	Google	Unassessed	197	819
H20 SXM ~	NVIDIA	Case-by-Case Review	148	4,000
H20E (HBM3E refresh) ~	NVIDIA	Unassessed	148	—
AMD Instinct MI400 ~	AMD	Restricted	—	19,600
AWS Trainium3 ~	Amazon	Unassessed	—	4,900
B30A ~	NVIDIA	Designed Compliant	—	—
Gaudi 2 ~	Intel	Restricted	—	2,450
Google TPU v7 (Ironwood)	Google	Unassessed	—	7,370
Huawei Ascend 910D ~	Huawei	Domestic (China)	—	—
NVIDIA B300	NVIDIA	Restricted	—	8,000
Tenstorrent Blackhole p150	Tenstorrent	Unassessed	—	512
Cerebras WSE-3 · Wafer-scale system; not plotted	Cerebras	Unassessed	—	21,000,000
Tenstorrent Wormhole n300 · Two-chip board totals; not plotted	Tenstorrent	Unassessed	131	576

ReadingDense FP16/BF16 compute is in TFLOPS; memory bandwidth is in GB/s. Board and wafer-scale totals appear last, outside the per-chip throughput ordering.

Explore a different TPP threshold

Threshold: TPP 4,800

At the 3A090.a.1 threshold.

27 of 31

Accelerators with a calculable TPP meet or exceed this threshold.

Accelerators above the threshold with a recorded China status other than “Restricted” (ringed) — Blackhole p150 (unassessed), Ascend 910B (domestic (china)), TPU v5p (unassessed), Ascend 910C (domestic (china)), B30A (designed compliant), Ascend 920 (domestic (china)) and 5 more.

Nearest below the line: TPU v4 at TPP 4,400 (8.3% below the parameter). Nearest above: A100 SXM at TPP 4,992 (4% above the parameter).

TPP uses dense throughput at each chip’s highest published basis under ECCN 3A090 (88 FR 73458); the default threshold is 4,800. Board totals and peaks without a verified dense basis are excluded.

TPP could not be calculated for Gaudi 2, Cerebras WSE-3, Tenstorrent Wormhole n300, Huawei Ascend 910D from the available specifications. ECCN 3A090.a.2 also covers TPP ≥ 1,600 with performance density ≥ 5.92. This calculation requires applicable die area, which is unavailable in this dataset. Chips below 4,800 TPP may therefore still meet that criterion.

Accelerator specifications and export status

35 accelerators · 12 have estimated specifications

Loading accelerators…

Chip families and compliance variants

Compare adjacent models

Comparison 1 · NVIDIA Ampere

FromA100 SXMRestricted

ToA800Restricted

Changed specifications
Measure	From	To	Unit
Interconnect	600	400	GB/s

The later model is recorded as a compliance variant of the earlier model.

A100 SXM source ↗A800 source ↗

Families tracked, 35 parts in all; the longest lane is NVIDIA Hopper with 8 models.

Compliance variants designed to meet export-control thresholds. Arcs connect variants to their parent chips across intervening models.

Adjacent model pairs with different recorded China export statuses.

Chips newly restricted by one of the listed actions; the year appears below each chip.

NVIDIA Ampere NVIDIA

A100 SXM312 TFLOPS dense · Restricted · newly restricted 2022
A800312 TFLOPS dense · Restricted · newly restricted 2023

NVIDIA Hopper NVIDIA

H100 SXM5989.5 TFLOPS dense · Restricted · newly restricted 2022
H100 PCIe756 TFLOPS dense · Restricted
H100 NVL835.5 TFLOPS dense · Restricted
H800 SXM5989.5 TFLOPS dense · Restricted · newly restricted 2023 · estimated specifications
H800 PCIe756 TFLOPS dense · Restricted · newly restricted 2023
H200 SXM989.5 TFLOPS dense · Case-by-Case Review
H20 SXM148 TFLOPS dense · Case-by-Case Review · newly restricted 2025 · estimated specifications
H20E (HBM3E refresh)148 TFLOPS dense · Unassessed · estimated specifications

NVIDIA Blackwell NVIDIA

B1001,750 TFLOPS dense · Restricted
B2002,250 TFLOPS dense · Restricted
NVIDIA B300no dense FP16/BF16 figure published · Restricted
B30Ano dense FP16/BF16 figure published · Designed Compliant · estimated specifications

NVIDIA Rubin NVIDIA

NVIDIA Rubin GPU4,000 TFLOPS dense · Restricted · estimated specifications

AMD Instinct AMD

MI300X1,307.4 TFLOPS dense · Restricted
MI325X1,307.4 TFLOPS dense · Case-by-Case Review
MI350X2,309.6 TFLOPS dense · Restricted
AMD Instinct MI355X2,516.6 TFLOPS dense · Restricted
AMD Instinct MI400no dense FP16/BF16 figure published · Restricted · estimated specifications

Huawei Ascend Huawei

Ascend 910B375 TFLOPS dense · Domestic (China) · estimated specifications
Huawei Ascend 910C780 TFLOPS dense · Domestic (China) · estimated specifications
Huawei Ascend 910Dno dense FP16/BF16 figure published · Domestic (China) · estimated specifications
Huawei Ascend 920900 TFLOPS dense · Domestic (China) · estimated specifications

Intel Gaudi Intel

Gaudi 2no dense FP16/BF16 figure published · Restricted · estimated specifications
Gaudi 31,835 TFLOPS dense · Restricted

Google TPU Google

Google TPU v4275 TFLOPS dense · Unassessed
TPU v5e197 TFLOPS dense · Unassessed
Google TPU v5p459 TFLOPS dense · Unassessed
Google TPU v6e (Trillium)918 TFLOPS dense · Unassessed
Google TPU v7 (Ironwood)no dense FP16/BF16 figure published · Unassessed

AWS Trainium Amazon

AWS Trainium3no dense FP16/BF16 figure published · Unassessed · estimated specifications

Cerebras Wafer-Scale Engine Cerebras

Cerebras WSE-3no dense FP16/BF16 figure published · Unassessed · wafer-scale figures

Tenstorrent Tenstorrent

Tenstorrent Wormhole n300131 TFLOPS dense · Unassessed · two-chip board totals
Tenstorrent Blackhole p150no dense FP16/BF16 figure published · Unassessed

Each row groups a chip family in catalog order; spacing does not represent elapsed time. Numbered controls select adjacent-model comparisons; individual chip names open their full specifications. Arrows identify recorded compliance variants.

Control rules and policy changes

2022-10-21October 2022 Advanced Computing Rule87 FR 62186
Compute performance (TFLOPS) and interconnect bandwidth
ECCN 3A090 combined an aggregate bidirectional transfer rate of at least 600 GB/s to or from other ICs, excluding volatile memories, with compute criteria equivalent to at least 4,800 bits × TOPS. Both bandwidth and compute conditions had to be met.
Oct 2022 interconnect threshold (600 GB/s) — 600 GB/s
Newly restricted: A100 SXM, H100 SXM5.
2023-11-17October 2023 Advanced Computing Update88 FR 73458
Total Processing Performance (TPP): 2 × MacTOPS × bit-length, summed across processing units
Introduced the TPP metric — dense throughput × bit-length of the operation, evaluated at the highest value across supported bit-lengths, dense matrices only. Closed the A800/H800 interconnect-reduction loophole. Also broadened end-use controls. 3A090.a also has a second leg (TPP ≥ 1,600 with performance density ≥ 5.92) that requires applicable die area, which no record here publishes.
ECCN 3A090.a — 4,800 TPP (2 × MacTOPS × bit-length; verified against 88 FR 73458 and the current CCL)
Newly restricted: A800, H800 SXM5, H800 PCIe.
2024-12-02December 2024 Expansion89 FR 96790
HBM memory bandwidth density
Added ECCN 3A090.c for HBM above 2 GB/s/mm² of memory bandwidth density, calculated from package or stack bandwidth and area. Certain co-packaged HBM-and-logic ICs whose dominant function is processing are excluded. The rule took effect December 2; compliance with the HBM provisions began December 31, 2024.
No newly restricted chips are recorded here for this action.
2025-04-09April 2025 H20 License RequirementNVIDIA Form 8-K
No new threshold metric. License-required determination on the previously-compliant-by-design H20.
NVIDIA reported an April 9 government notice requiring licenses for H20 and other ICs meeting specified H20 bandwidth characteristics. It covered exports to China, including Hong Kong and Macau, D:5 countries, and companies headquartered or with an ultimate parent there. NVIDIA disclosed the notice on April 15.
Newly restricted: H20 SXM.
2025-07-14July 2025 H20 Licensing AnnouncementNVIDIA announcement NVIDIA August 2025 filing
Announcement of expected licensing; no technical threshold change.
NVIDIA announced assurances that licenses would be granted. Its August 2025 filing later confirmed licenses for selected H20 customers, and described a 15% revenue-share expectation from U.S. officials with no codifying regulation at that time.
No newly restricted chips are recorded here for this action.
2026-01-15January 2026 License Review Policy Revision91 FR 1684
Conditional case-by-case licensing pathway for H200-class chips.
Provides case-by-case review for qualifying US exports to China or Macau below 21,000 TPP and 6,500 GB/s total DRAM bandwidth. H200 and MI325X are examples. Approval depends on the rule’s supply, aggregate-TPP, end-use, security and testing conditions.
No newly restricted chips are recorded here for this action.

Changes within each family

NVIDIA Ampere NVIDIA: A800 reduced A100 interconnect bandwidth while retaining its compute throughput. The October 2023 revision removed interconnect bandwidth as a control parameter and restricted A800.
NVIDIA Hopper NVIDIA: H800 reduced interconnect bandwidth; H20 instead reduced compute while retaining substantial memory and interconnect bandwidth. The policy history includes restrictions on H800, a separate H20 licensing requirement and conditional case-by-case review for H200. Model details distinguish these actions and their dates.
NVIDIA Blackwell NVIDIA: B100 and B200 differ in power and throughput. B300 Blackwell Ultra raises dense FP4 throughput and memory capacity; B30A was reported as a proposed single-die variant for China, with specifications that remain estimates.
NVIDIA Rubin NVIDIA: Rubin GPU preliminary individual-GPU specifications: 35 PFLOPS dense NVFP4 training, 17.5 PFLOPS dense FP8/FP6 training, 4 PFLOPS dense FP16/BF16, 288 GB HBM4 at 22 TB/s, and 3.6 TB/s NVLink. NVIDIA marks the figures as up to and subject to change.
AMD Instinct AMD: MI325X expands memory relative to MI300X. The CDNA 4 MI350X and MI355X differ in cooling and throughput: MI350X is air-cooled, MI355X liquid-cooled. Their datasheets distinguish dense from sparse performance; the table uses dense values. MI400 specifications remain estimates from AMD’s June 2025 announcement.
Huawei Ascend Huawei: The 910B entry represents CSET’s 910B2 variant. The 910C estimate differs from Epoch AI’s reported throughput; 910D lacks numerical compute specifications here. The cited 920 report describes a projected launch. These differences in evidence limit comparisons across the family.
Intel Gaudi Intel: Gaudi 2 and Gaudi 3 use Ethernet interconnects. Gaudi 3 combines TSMC N5 compute dies with Intel EMIB packaging. Its OAM and PCIe variants have different power ratings; this table represents the OAM variant.
Google TPU Google: TPU v5e targets efficiency; v5p expands memory and interconnect bandwidth for training. Trillium and Ironwood increase compute throughput, with Ironwood reported at FP8. TPU v4’s recorded power is a measured mean; per-chip power is unavailable here for Ironwood.
AWS Trainium Amazon: Trainium3 powers EC2 Trn3 UltraServers, which AWS announced as generally available in December 2025. Access is offered through AWS services. Per-chip power is not supplied in the cited announcement.
Cerebras Wafer-Scale Engine Cerebras: WSE-3 uses wafer-scale integration and on-wafer SRAM. Its wafer-wide compute and bandwidth figures require separate treatment from per-GPU specifications.
Tenstorrent Tenstorrent: Wormhole n300 is a dual-ASIC PCIe card. Blackhole p150 uses the second-generation Tensix architecture with Ethernet scale-out. Its published compute figure uses BLOCKFP8; no dense FP16/BF16 figure is held here.

How a chip is classified

Under the October 2023 Advanced Computing Update, TPP is 2 × MacTOPS × bit-length, summed across processing units (88 FR 73458). For dense FP16, this is 16 times the published TFLOPS. The calculation uses the highest TPP available across each chip’s published bit-lengths, and each result is compared with the ECCN 3A090.a threshold of 4,800. Licensing also depends on the transaction and the other applicable controls.

9 of the 35 accelerators have no dense FP16/BF16 specification in this dataset; other published precisions can still support a TPP calculation. TPP cannot be evaluated for 4 chips, which publish no dense per-IC figure.

6 accelerators are offered through Google Cloud or AWS, and the cited product documentation classifies none of them for China export. 4 have a dense-FP16/BF16-based TPP above the H20 SXM’s 2,368, the lowest such reading among chips newly restricted by the actions listed here.

For restrictions on semiconductor manufacturing equipment, see supply-chain chokepoints.

Memory

Process

NVIDIA Rubin GPU

NVIDIA

4,000

22,000

288 GB HBM4

—

Restricted

AMD Instinct MI355X

AMD

2,516.6

8,000

288 GB HBM3E

TSMC N3P + N6

Restricted

MI350X

AMD

2,309.6

8,000

288 GB HBM3E

TSMC N3P + N6

Restricted

B200

NVIDIA

2,250

8,000

192 GB HBM3E

TSMC 4NP

Restricted

Gaudi 3

Intel

1,835

3,700

128 GB HBM2e

TSMC 5nm

Restricted

B100

NVIDIA

1,750

8,000

192 GB HBM3E

TSMC 4NP

Restricted

MI300X

AMD

1,307.4

5,300

192 GB HBM3

TSMC 5nm/6nm

Restricted

H100 SXM5

NVIDIA

989.5

3,350

80 GB HBM3

TSMC 4N

Restricted

H800 SXM5 variant

NVIDIA

989.5

—

80 GB HBM3

TSMC 4N

Restricted

H100 NVL

NVIDIA

835.5

3,938

94 GB HBM3

TSMC 4N

Restricted

H100 PCIe

NVIDIA

756

2,000

80 GB HBM2e

TSMC 4N

Restricted

H800 PCIe variant

NVIDIA

756

2,000

80 GB HBM2e

TSMC 4N

Restricted

A100 SXM

NVIDIA

312

2,039

80 GB HBM2e

TSMC 7nm

Restricted

A800 variant

NVIDIA

312

2,039

80 GB HBM2e

TSMC 7nm

Restricted

AMD Instinct MI400

AMD

—

19,600

432 GB HBM4

—

Restricted

Gaudi 2

Intel

—

2,450

96 GB HBM2e

TSMC 7nm

Restricted

NVIDIA B300

NVIDIA

—

8,000

288 GB HBM3E

TSMC N4

Restricted

MI325X

AMD

1,307.4

6,000

256 GB HBM3E

TSMC 5nm/6nm

Case-by-Case Review

H200 SXM

NVIDIA

989.5

4,800

141 GB HBM3E

TSMC 4N

Case-by-Case Review

H20 SXM variant

NVIDIA

148

4,000

96 GB HBM3

TSMC 4N

Case-by-Case Review

FP16 dense148 TFLOPS

FP16 sparse296 TFLOPS

BF16 dense148 TFLOPS

TF32 dense74 TFLOPS

TF32 sparse148 TFLOPS

FP8 dense296 TFLOPS

FP8 sparse592 TFLOPS

FP4 dense—

FP4 sparse—

INT8296 TOPS

Memory96 GB HBM3

Memory bandwidth4,000 GB/s

Interconnect bandwidth900 GB/s

Thermal design power400 W

Process nodeTSMC 4N

ArchitectureHopper

Compliance variant ofH100 SXM5

Total Processing Performance2,368 (FP16 × bit-length; ≈0.493× the 3A090.a parameter)

Regulatory basis

NVIDIA reports that U.S. licenses for selected H20 sales began in August 2025.

Status source

Conditions

NVIDIA’s August 2026 filing says Chinese government restrictions prevented it from selling its H20 inventory despite those licenses.

Source

Press or analyst IFP "The H20 Problem" (Apr 2025) + Tom's Hardware H20 reporting + Flopper.io spec sheet + Baidu Baike English mirror + SemiAnalysis (Nov 2023). NO public NVIDIA H20 datasheet exists — H20 is sold via Chinese OEM channels (H3C / Inspur / Sugon) only. — open

Notes

Hopper compliance variant designed after the October 2023 rule. Reported specifications include 96 GB HBM3, 4 TB/s memory bandwidth and 900 GB/s NVLink. The figures come from secondary sources. Sparse throughput values are derived by applying a 2× multiplier to dense throughput; they are not separately reported measurements.

Recorded deployments

This accelerator is not named in the GPU inventories held for 9 facilities.

Country access

Not covered in the 26 country access profiles. Browse country coverage.

B30A variant

NVIDIA

—

144 GB HBM3E

TSMC (node unconfirmed)

Designed Compliant

Huawei Ascend 920

Huawei

900

4,000

—

SMIC N+3 (6nm-class)

Domestic (China)

Huawei Ascend 910C

Huawei

780

3,200

128 GB HBM

SMIC N+2 (~7nm class, 2nd-gen)

Domestic (China)

Ascend 910B

Huawei

375

1,600

64 GB HBM2e

SMIC N+2 (~7nm class, 2nd-gen)

Domestic (China)

Huawei Ascend 910D

Huawei

—

5nm

Domestic (China)

Google TPU v6e (Trillium)

Google

918

1,638

32 GB HBM

—

Unassessed

Google TPU v5p

Google

459

2,575

95 GB HBM2e

—

Unassessed

Google TPU v4

Google

275

1,200

32 GB HBM2

7nm

Unassessed

TPU v5e

Google

197

819

16 GB HBM2e

—

Unassessed

H20E (HBM3E refresh) variant

NVIDIA

148

—

144 GB HBM3E

TSMC 4N

Unassessed

AWS Trainium3

Amazon

—

4,900

144 GB HBM3E

TSMC N3

Unassessed

Cerebras WSE-3

Cerebras

—

21,000,000 †

44 GB On-chip SRAM

TSMC 5nm

Unassessed

Google TPU v7 (Ironwood)

Google

—

7,370

192 GB HBM3E

—

Unassessed

Tenstorrent Blackhole p150

Tenstorrent

—

512

32 GB GDDR6

—

Unassessed

Tenstorrent Wormhole n300

Tenstorrent

131 †

576 †

24 GB GDDR6

—

Unassessed