Compute Leverage
Leverage over a frontier training run, measured as switching cost times redeployment time.
Leverage over a frontier training run, measured as switching cost times redeployment time.
The reach of the check. Every link a frontier training run passes through, in the order it passes them. A solid mark is a link where one holder can stall the run for a year or more; a hollow mark is one where it cannot, because a production alternative already exists. For each of the eight that can stall it, the bands show what the check over that layer is able to do — refuse supply, decide who is served, or both. The two are different powers and the figure keeps them apart deliberately: a rule that can forbid a shipment to the wrong buyer is not a rule that can put a lab at the front of the queue. What is drawn from the substrate is the holder, the verdict and the KIND of check; what each kind of check can do is Scrutica’s reading of that kind, written once and applied to every layer that has it — it is not a field in the record, and a reader who disagrees with the reading can see exactly which rows it moves. No band is drawn for the three links that are not chokepoints: a check over something nobody is waiting on is not a finding.
Training a frontier model runs through a long supply chain: the software the chips are designed on, the handful of machines that can pattern them, the fabs that print them, the packaging that fuses them, and the power to run it all. At eight points along that chain a single holder can stall the work for a year or more. Every one of the eight sits under some check — which is the reassuring half of the finding, and not the half that matters. The check that reaches seven of them is export-control law, and what export-control law does is decide where a holder may sell. It does not decide that a holder must sell, or to whom. For a lab trying to field the next run, that second question is the whole question, and exactly one of the eight chokepoints has anything standing over it that can answer it: grid power, where the holders are public bodies running a queue.
The narrowest of the eight is advanced packaging — the step that fuses bare silicon and memory into a working accelerator, held by TSMC and OSATs (ASE, Amkor, SPIL). Until January 2025 no export rule reached it at all. One now does: the BIS due-diligence rule for advanced computing chips (90 FR 5298) makes approved-packager attestations the mechanism by which packaged advanced chips escape a licensing presumption, and requires quarterly compliance reporting to Washington. It took effect on 16 January 2025 and bound exporters from 31 January — the rule states the two dates separately, and the second is the one at which anybody had to do anything.
Read it for what it does. It polices where finished chips end up. It says nothing about who gets the packaging capacity in the first place — and packaging capacity is allocated years out, which means for the next frontier run the allocation is the binding decision and the rule does not touch it. That decision answers to the customers already in the queue. This is the shape of seven of the eight rows in the figure above, and it is why “the layer is checked” and “the layer is governed” are not the same sentence.
| Link in the chain | Can one holder stall the run? | What checks it | What that check can do |
|---|---|---|---|
| Chip-design software · the toolchains every leading-edge chip is designed on — Synopsys, Cadence, Siemens EDA | Yes | Export-control law | Stop a sale |
| Chip lithography · the machines that pattern leading-edge chips — ASML | Yes | Export-control law | Stop a sale |
| Leading-edge fabrication · the fabs that print the smallest transistors — TSMC, Samsung Foundry, Intel Foundry | Yes | Export-control law | Stop a sale |
| High-bandwidth memory · the stacked memory every accelerator needs — SK Hynix, Samsung, Micron | Yes | Export-control law | Stop a sale |
| Advanced packaging · the step that fuses bare silicon into a working accelerator — TSMC, OSATs (ASE, Amkor, SPIL) | Yes | Export-control law | Stop a sale |
| AI accelerators · the chips that do the training — NVIDIA, Google TPU, AWS Trainium, AMD | Yes | Export-control law | Stop a sale |
| In-server interconnect · the high-speed links between chips in one box — NVIDIA | Yes | Export-control law | Stop a sale |
| Grid power · getting hundreds of megawatts connected — ISO/RTO (MISO, PJM, ERCOT, SPP), local utility, state PUC, FERC, EPA | Yes | Public bodies | Refuse a connection, and decide who is served |
| Between-server networking · the fabric that ties thousands of boxes into one machine — NVIDIA/Mellanox InfiniBand, Broadcom/Arista Ethernet | No — a production alternative exists | A market rival | Neither — a rival is a substitute, not a check |
| Data-center capacity · somewhere built to house the machines — AWS, Microsoft Azure, Google Cloud, CoreWeave, Oracle, neoclouds | No — a production alternative exists | A market rival | Neither — a rival is a substitute, not a check |
| Capital · the money a single run costs — hyperscaler balance sheets, sovereign funds (QIA, PIF, Mubadala), mega-VC | No — a production alternative exists | A market rival | Neither — a rival is a substitute, not a check |
Most of the eight loosen within five years as rivals qualify. Two do not — chip-design software and chip lithography — where no second supplier is in sight at any horizon a Western lab could reach. That is a claim about how markets mature rather than a measurement, and the Leverage view draws it as a slope with the evidence grade of every coefficient marked on the line, including the ones for which no published figure was found.
This is the brief. The Leverage view has the full instrument: every holder, the switching cost and redeployment time behind each verdict, the rule that assigns each check, the per-field sources, and the same counts resolved against a specific lab’s run rather than the cross-run default.