# Compute Governance Glossary ## 77 terms across 8 domains The terms the site uses, each defined once. Definitions and standardization notes for the terms the methodology and the instruments use: semiconductor manufacturing, AI training hardware, export controls, and compute policy. Each entry says what the term means and why it matters for governance, beyond what it expands to. Search glossary terms AllSemiconductor ManufacturingGPU / Accelerator ArchitectureAI TrainingData CentersSupply ChainExport ControlsGovernanceMethodology 77 terms ## Semiconductor Manufacturing Semiconductor Manufacturing15 terms ### EUV lithography (EUV) Extreme ultraviolet lithography uses 13.5 nm wavelength light to pattern features below 7 nm on silicon wafers. Requires a tin-droplet plasma source, multilayer mirrors, and vacuum-sealed optical path. Related: DUV lithography · Photomask · Process node ### DUV lithography (DUV) Deep ultraviolet lithography uses 193 nm (ArF) or 248 nm (KrF) wavelength light. Multi-patterning techniques extend DUV to ~7 nm nodes at the cost of additional process steps and yield loss. Related: EUV lithography · Multi-patterning · Process node ### Process node A named manufacturing generation (e.g., N4, N5, N7) indicating transistor density and power characteristics. Modern node names are marketing labels; actual gate lengths differ from the stated nanometer value. Related: EUV lithography · FinFET · GAA ### Wafer A thin disc of crystalline silicon (typically 300 mm diameter) on which hundreds of chip dies are patterned simultaneously. Wafer starts per month is the standard measure of fab capacity. Related: Die · Yield · Foundry ### Yield The fraction of functional dies per wafer. Advanced-node yields typically start at 30-50% and improve to 80%+ over 12-18 months of production maturity. Related: Wafer · Die · Process node ### CoWoS Chip-on-Wafer-on-Substrate: TSMC's 2.5D advanced packaging technology that places multiple chiplets and HBM stacks on a silicon interposer. Critical bottleneck for AI accelerators. Related: HBM · Interposer · Advanced packaging ### HBM High Bandwidth Memory: vertically stacked DRAM dies connected by through-silicon vias (TSVs). HBM3e provides ~4.8 TB/s bandwidth per stack. Required for modern AI accelerators. Related: CoWoS · Memory bandwidth · SK Hynix ### Foundry A semiconductor manufacturer that fabricates chips designed by other companies (fabless firms). TSMC, Samsung Foundry, and GlobalFoundries are the major foundries. Related: Fabless · IDM · Wafer ### Fabless A chip company that designs but does not manufacture its own chips. NVIDIA, AMD, Qualcomm, and Apple are fabless; they rely on foundries for production. Related: Foundry · IDM ### IDM Integrated Device Manufacturer: a company that both designs and fabricates its own chips. Intel, Samsung, and Texas Instruments are IDMs. Related: Foundry · Fabless ### OSAT Outsourced Semiconductor Assembly and Test: companies that package and test fabricated chips. ASE, Amkor, and JCET are major OSATs. Related: CoWoS · Advanced packaging ### FinFET Fin Field-Effect Transistor: a 3D transistor architecture where the gate wraps around a raised "fin" of silicon. Used at 14nm through 3nm nodes. Related: GAA · Process node ### GAA Gate-All-Around transistor: the successor to FinFET where the gate completely surrounds the channel. Samsung and TSMC are transitioning to GAA at 2nm and below. Related: FinFET · Process node ### Photomask A quartz plate with patterned chrome features that defines the circuit layout projected onto the wafer during lithography. A single advanced chip design requires 80-100 mask layers. Related: EUV lithography · DUV lithography ### Advanced packaging Post-fabrication techniques (CoWoS, InFO, EMIB, Foveros) that integrate multiple chiplets and memory stacks into a single package. Enables the large-die configurations required for AI accelerators. Related: CoWoS · HBM · Chiplet ## GPU / Accelerator Architecture GPU / Accelerator Architecture11 terms ### FLOP Floating-point operation: a single arithmetic operation (add, multiply) on a floating-point number. FLOP/s (per second) measures raw compute throughput; total FLOP measures cumulative compute used for training. Related: TFLOP/s · Training compute · FP16 ### TFLOP/s Tera (10¹²) floating-point operations per second. The standard unit for GPU compute throughput. H100 SXM: 989.5 TFLOP/s FP16 dense, 1,979 TFLOP/s with 2:4 structured sparsity. Related: FLOP · FP16 · BF16 ### FP16 Half-precision 16-bit floating-point format. Most AI training uses FP16 or BF16 arithmetic; FLOP/s benchmarks for AI typically report FP16 throughput. Related: BF16 · FP8 · TFLOP/s ### BF16 Brain floating-point 16-bit format: same total bits as FP16 but with 8 exponent bits (matching FP32) and 7 mantissa bits. Preferred for training stability. Related: FP16 · FP8 ### TDP Thermal Design Power: the maximum sustained power draw of a chip in watts. H100 SXM: 700W; H100 PCIe: 350W; H200 SXM: 700W; B200: 1,000W. Related: PUE · GPU cluster ### NVLink NVIDIA's proprietary high-bandwidth GPU-to-GPU interconnect. NVLink 4.0 (Hopper) provides 900 GB/s bidirectional bandwidth; NVLink 5.0 (Blackwell) provides 1,800 GB/s. Related: InfiniBand · GPU cluster · Interconnect fabric ### InfiniBand High-bandwidth, low-latency networking fabric used to connect GPU nodes in AI training clusters. NVIDIA (via Mellanox acquisition) dominates the AI-grade InfiniBand market. Related: NVLink · Interconnect fabric · GPU cluster ### Tensor core Specialized matrix-multiply units in NVIDIA GPUs that perform mixed-precision fused multiply-add operations. Responsible for the majority of AI training throughput. Related: TFLOP/s · FP16 · BF16 ### Memory bandwidth The data transfer rate between GPU compute units and memory, measured in TB/s. H100 SXM: 3.35 TB/s; H200 SXM: 4.8 TB/s (with HBM3e). Related: HBM · TFLOP/s ### SXM NVIDIA's server-grade GPU form factor with direct NVLink connectivity. SXM variants (H100 SXM, B200 SXM) offer higher power limits and bandwidth than PCIe equivalents. Related: PCIe · NVLink · TDP ### PCIe PCI Express: the standard expansion bus interface. PCIe GPUs (e.g., H100 PCIe) have lower TDP (350W vs. 700W) and no NVLink, limiting large-scale training capability. Related: SXM · NVLink ## AI Training AI Training8 terms ### Training compute The total floating-point operations used to train a model, measured in FLOP. Distinct from inference compute (running a trained model) and fine-tuning compute. Related: FLOP · Inference · Scaling law ### Inference Running a trained model to produce outputs (predictions, text, images). Inference compute per query is orders of magnitude smaller than total training compute, but aggregate inference demand can exceed training demand. Related: Training compute · FLOP ### Scaling law Empirical power-law relationship between training compute, dataset size, model parameters, and model performance. Kaplan et al. (2020) and Hoffmann et al. (2022, "Chinchilla") established key scaling relationships. Related: Training compute · Chinchilla-optimal · Parameter count ### Chinchilla-optimal A training configuration that balances model size and dataset size according to the Hoffmann et al. (2022) scaling law. Chinchilla-optimal models use ~20 tokens per parameter. Related: Scaling law · Training compute · Parameter count ### Parameter count The number of trainable weights in a neural network. GPT-4 is widely reported (Tier 3, analyst estimates; OpenAI has not confirmed) at ~1.8 trillion parameters (MoE). Larger parameter counts require more memory and compute. Related: Training compute · Scaling law · FLOP ### MFU Model FLOP Utilization: the fraction of theoretical peak GPU throughput actually achieved during training. Typical values: 30-50% for large clusters. Higher MFU means more efficient hardware utilization. Related: Training compute · GPU cluster · Interconnect fabric ### Fine-tuning Continued training of a pre-trained model on a smaller, task-specific dataset. Uses 100-10,000x less compute than the original pre-training run. Related: Training compute · Inference ### METR time horizon (METR) Model Evaluation and Threat Research benchmark measuring how long an AI agent can autonomously work on real-world tasks. Scored on a 0-5 scale corresponding to task durations from seconds to weeks. Related: Training compute · FLOP ## Data Centers Data Centers8 terms ### PUE Power Usage Effectiveness: ratio of total facility power to IT equipment power. PUE 1.0 = all power goes to compute; PUE 1.2 = 20% overhead for cooling, lighting, networking. Industry average: ~1.3. Related: TDP · GPU cluster · Liquid cooling ### MW Megawatt: 1 million watts. The standard measure of data center power capacity. A 100 MW facility can host roughly 100,000-140,000 H100 GPUs at full load (accounting for PUE). Related: PUE · TDP · Utilization rate ### Liquid cooling Direct-to-chip or immersion cooling that removes heat more efficiently than air cooling. Required for GPUs above ~400W TDP (Blackwell B200 at 1,000W mandates liquid cooling). Related: PUE · TDP ### GPU cluster A set of GPU servers connected by high-bandwidth networking (NVLink + InfiniBand) that can collectively train a single model. Modern frontier clusters contain 10,000-100,000+ GPUs. Related: NVLink · InfiniBand · MFU ### Utilization rate The fraction of installed GPU capacity actively performing compute, averaged over time. Typical values: 50-80% for training workloads. Affected by scheduling, maintenance, and workload mix. Related: GPU cluster · MFU ### Interconnect fabric The network infrastructure connecting GPU nodes within a cluster. Combines NVLink (intra-node), InfiniBand or Ethernet (inter-node), and spine-leaf topology for scalable bandwidth. Related: NVLink · InfiniBand · GPU cluster ### Neocloud GPU cloud providers (CoreWeave, Lambda, Nebius, Applied Digital, IREN) that rent compute capacity without the broad cloud services offered by hyperscalers (AWS, GCP, Azure). Related: GPU cluster · Sole-source dependency ### Hyperscaler Cloud providers operating at massive scale: Amazon (AWS), Microsoft (Azure), Google (GCP), Meta, Oracle. Characterized by >100 MW data center campuses, custom silicon programs, and global infrastructure. Related: Neocloud · GPU cluster · MW ## Supply Chain Supply Chain8 terms ### Sole-source dependency A supply chain relationship where only one company produces a critical input. ASML for EUV machines, TSMC for advanced-node foundry services, and Zeiss for EUV optics are sole-source dependencies. Related: Chokepoint · Supply chain edge ### Supply chain edge A directed relationship between two entities in the supply chain graph. Edges have attributes: relationship type (supplier/customer/partner), value ($M), and source (licensed supply-chain database or SEC filing). Related: Supply chain centrality · Licensed supply-chain database ### HHI Herfindahl-Hirschman Index: the sum of squared market shares. Ranges from near 0 (perfect competition) to 10,000 (monopoly). Calculated as HHI = sum(s\_i^2) where s\_i is each firm's percentage market share. Related: Sole-source dependency · Chokepoint ### Chokepoint A supply chain node where concentration or sole-source dependency creates a governance-relevant bottleneck. Measured by HHI, node centrality, and substitutability assessment. Related: Sole-source dependency · HHI · Cascade ### Cascade The propagation of a disruption through supply chain relationships. Modeled via breadth-first search across the relationship graph with decay factors based on supply share and criticality. Criticality can be editorial (1-10 replaceability scale) or blended with a 3-month price correlation where available. Blend formula: adjustedCriticality = w × 5(1+r) + (1-w) × editorial. Related: Chokepoint · Supply chain edge · BFS ### Licensed supply-chain database A licensed institutional supply-chain relationship database, held under subscription and not redistributed. Contains bilateral supplier-customer links with relationship value ($M), relationship rank, and 3-month rolling stock price correlation. Authority tier 2: the underlying facts (who supplies whom) are surfaced; the vendor records themselves are not republished. Related: Supply chain edge · Price correlation ### Price correlation The 3-month rolling Pearson correlation between two companies' stock prices, stored on the licensed supply-chain database edges. Available on ~78% of those edges. Used to modulate cascade criticality scores when market correlation weighting is enabled. Maps r to the \[1,10\] criticality scale via 5×(1+r) and blends with editorial scores at a configurable weight (default 0.5). Edges without a correlation value and unlisted companies fall back to editorial criticality. Related: Cascade · Licensed supply-chain database · Supply chain edge ### Substitutability Expert-assessed score (0-1) indicating how easily a disrupted supplier can be replaced. 0 = no substitute exists (ASML for EUV); 1 = drop-in replacements available. Authority tier 3 (analyst assessment). Related: Cascade · Decay rate · Chokepoint ## Export Controls Export Controls9 terms ### EAR Export Administration Regulations: the US legal framework governing export of dual-use items. Administered by BIS (Bureau of Industry and Security). Key classifications: 3A090 (advanced computing ICs), 4A090 (computers containing 3A090 chips). Related: Entity List · License exception · BIS ### Entity List A BIS-maintained list of foreign entities subject to specific export restrictions. Inclusion requires a license for most items subject to the EAR, with a presumption of denial for advanced computing. Related: EAR · BIS · License exception ### BIS Bureau of Industry and Security: the US Department of Commerce agency that administers export controls. Issues licenses, maintains the Entity List, and promulgates rules under the EAR. Related: EAR · Entity List ### License exception An authorization under the EAR that permits export without an individual license when specified conditions are met. Examples: License Exception TSR (technology/software under restriction), ACE (authorized cybersecurity exports). Related: EAR · BIS ### Deemed export Transfer of controlled technology to a foreign national within the United States. Governed by the same EAR classifications as physical exports. Related: EAR · BIS ### Wassenaar Arrangement A multilateral export control regime with 42 participating states. Sets baseline control lists for conventional arms and dual-use technologies, including semiconductor equipment and advanced computing. Related: EAR · End-use controls ### End-use controls Export restrictions based on the intended application rather than the item's technical specifications. Applied when there is knowledge or reason to believe the item will be used for a prohibited purpose. Related: EAR · Entity List ### De minimis rule EAR provision that exempts foreign-made items containing less than a specified percentage (typically 25%) of controlled US-origin content. Threshold varies by destination and item. Related: EAR · Entity List ### TOPS Tera operations per second: the performance metric used in US export control rules to determine whether a chip is "advanced." The October 2022 rule set thresholds at 300 TOPS (for certain interconnect bandwidth) and 600 TOPS. Related: EAR · TFLOP/s ## Governance Governance8 terms ### GPAI General-purpose AI: the category defined by the EU AI Act for models trained on broad data that can perform a wide range of tasks. Models trained above 10²⁵ FLOP are classified as GPAI with systemic risk. Related: FLOP · Training compute · EU AI Act ### Systemic risk Under the EU AI Act, the risk classification for GPAI models with "high-impact capabilities" (currently proxied by training compute above 10²⁵ FLOP). Triggers additional obligations: red-teaming, incident monitoring, cybersecurity. Related: GPAI · FLOP · EU AI Act ### EU AI Act Regulation (EU) 2024/1689: the European Union's comprehensive AI regulation. Establishes risk-based classification, GPAI transparency requirements, and compute thresholds for systemic risk designation. Related: GPAI · Systemic risk · FLOP ### Compute governance The use of compute as a governance lever for AI policy. Based on the premise that compute is measurable, excludable, and concentrated — properties that make it a tractable intervention point. Related: FLOP · Training compute · GPAI ### Dual-use Technology with both civilian and military applications. All advanced AI chips are dual-use; the same GPU that trains a language model can train a military targeting system. Related: EAR · Wassenaar Arrangement ### Proliferation In the AI governance context: the spread of advanced AI capabilities to additional actors. Distinct from weapons proliferation but often analyzed with similar frameworks (supply-side controls, demand-side monitoring). Related: Dual-use · Compute governance ### Sovereign AI National programs to develop domestic AI compute capacity, independent of foreign hyperscalers. Includes government-funded GPU clusters, national cloud initiatives, and indigenous chip development. Related: Compute governance · GPU cluster ### Reality ratio Scrutica metric for sovereign AI programs: disbursed spending divided by the GOVERNMENT-ONLY announced figure (falling back to the all-capital headline only where no government-only figure is published). A reality ratio of 0.1 means 10% of the government's own commitment has reached operational deployment. It is deliberately not disbursed-over-headline: headline figures roll private capital in beside the government programme, so dividing by them measures announcement composition rather than execution. Related: Sovereign AI ## Methodology Methodology10 terms ### Confidence interval A range of values within which the true value is estimated to fall with a stated probability (typically 90%). Scrutica reports estimation bounds rather than point estimates where multiple estimation paths are available. Related: Estimation bounds · Authority tier ### Authority tier Scrutica's source credibility classification: Tier 1 (primary measurement/SEC filing), Tier 2 (research institution database), Tier 3 (press report/analyst estimate), Tier 4 (estimated/inferred). Related: Confidence interval · Provenance ### Provenance The documented origin and transformation history of a data point. Every Scrutica value has data\_source, source\_url, and is\_estimated fields. Related: Authority tier · is\_estimated ### is\_estimated A boolean flag on every Scrutica data point. True if the value is derived or inferred; false only if it comes from a primary source with direct measurement. Related: Authority tier · Provenance ### Estimation bounds The range produced by cross-validating multiple estimation paths. When hardware, power, and cost paths agree within 15%, confidence is high; when they diverge, the bounds are wide. Related: Confidence interval · Authority tier ### BFS propagation (BFS) Breadth-first search: a graph traversal algorithm used in the cascade simulator to model disruption spreading hop-by-hop through the supply chain. Each hop applies a decay factor based on edge substitutability. Related: Cascade · Supply chain edge ### Decay rate The per-hop reduction in disruption impact during cascade propagation. Calculated as 1 minus substitutability score, clamped at 0.8. Higher decay = faster attenuation = more resilient supply chain. Related: BFS propagation · Cascade ### Capex disaggregation Decomposing a company's total capital expenditure into components: land, buildings, power infrastructure, networking, GPU/accelerator hardware, and other IT equipment. Related: Estimation bounds · FLOP ### Petaflop-day (PF-day) One petaFLOP (10¹⁵ FLOP/s) sustained for one day (86,400 seconds) = 8.64 × 10¹⁹ FLOP. Used as the unit for the Compute Cost Index. Related: FLOP · TFLOP/s · SCU ### Scrutica Compute Unit (SCU) Scrutica's coinage for 1 petaFLOP-day of BF16 dense training compute (= 8.64 × 10¹⁹ FLOP). $/SCU is the platform's normalized cost metric: hourly instance price x 24 / (num\_gpus x BF16 dense TFLOP/s / 1000). BF16 dense throughput per GPU (989.5 for H100 SXM, 312 for A100, 2,250 for B200) comes from Epoch AI ML Hardware; the SCU normalization itself is not an Epoch metric. Related: Petaflop-day · TFLOP/s · BF16 · MFU