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# ASU NAPMP Fan-Out Wafer-Level Processing R&D Facility (Tempe AZ)

Facility record `fac-asu-napmp-tempe-az` — data source: ds-nist-chips-rd-office (https://www.nist.gov/news-events/news/2025/01/us-department-commerce-announces-14-billion-final-awards-support-next); authority tier 1

| Field | Value |
| --- | --- |
| Type | Packaging |
| Status | Announced |
| Location | Tempe, Arizona, US |
| Power capacity | not published MW |
| IT load | not published |
| GPU count | not published |
| Peak PFLOPS (FP16) | not published |
| Owner | not published |
| Operator | not published |
| Announced | 2025-01-16 |
| Operational | not published |

## Cite

> Scrutica, "ASU NAPMP Fan-Out Wafer-Level Processing R&D Facility (Tempe AZ)" (facility record), https://scrutica.com/facilities/fac-asu-napmp-tempe-az; data source: ds-nist-chips-rd-office; accessed 2026-08-25.

Full interactive record: https://scrutica.com/facilities/fac-asu-napmp-tempe-az · Methodology for derived values: https://scrutica.com/methodology#flop-estimation · All programmatic surfaces: https://scrutica.com/agents